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75A Synchronous Buck NexFET™ Smart Power Stage with DualCool Package

CSD95490Q5MC

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Product details

Parameters

VDS (V) 20 Power loss (W) 2.25 Ploss current (A) 30 Configuration PowerStage ID, continuous drain current at Ta=25degC (A) 75 Package (mm) SON5x6 DualCool PowerStage Operating temperature range (C) -55 to 150 open-in-new Find other Power stages

Features

  • 75-A Continuous Operating Current Capability
  • Over 95% System Efficiency at 30 A
  • High-Frequency Operation (up to 1.25 MHz)
  • Diode Emulation Function
  • Temperature Compensated Bi-Directional Current Sense
  • Analog Temperature Output
  • Fault Monitoring
  • 3.3-V and 5-V PWM Signal Compatible
  • Tri-State PWM Input
  • Integrated Bootstrap Switch
  • Optimized Dead Time for Shoot-Through Protection
  • High-Density QFN 5-mm × 6-mm Footprint
  • Ultra-Low-Inductance Package
  • System Optimized PCB Footprint
  • Thermally Enhanced Topside Cooling
  • RoHS Compliant – Lead-Free Terminal Plating
  • Halogen Free

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Description

The CSD95490Q5MC NexFET™ power stage is a highly optimized design for use in a high-power, high-density synchronous buck converter. This product integrates the driver IC and power MOSFETs to complete the power stage switching function. This combination produces high-current, high-efficiency, and high-speed switching capability in a small 5-mm × 6-mm outline package. It also integrates the accurate current sensing and temperature sensing functionality to simplify system design and improve accuracy. In addition, the PCB footprint has been optimized to help reduce design time and simplify the completion of the overall system design.


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More Information and Sample Availability

Full data sheet and other information are available. Request now

Samples are available (CSD95490Q5MC and CSD95490Q5MCT). Request now

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 6
Type Title Date
* Datasheet CSD95490Q5MC Synchronous Buck NexFET Smart Power Stage datasheet (Rev. A) Jan. 09, 2018
Technical articles Sequencing and powering FPGAs in radar and other defense applications Nov. 18, 2019
Application note Multiphase Buck Design from Start to Finish, Part 1 (Rev. A) May 24, 2019
Technical articles Understanding the benefits of “lead-free” power MOSFETs Feb. 07, 2019
Technical articles How to use PMBus power solutions for NXP QorIQ processors May 09, 2018
Technical articles Signal integrity in multiphase, smart power-stage applications Oct. 10, 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION MODEL Download
SLPM296.ZIP (42 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
Switched capacitor integrated buck (SCIB) power converter reference design
PMP22510 — This switched capacitor integrated buck (SCIB) converter is a highly-optimized design for use in a high-power, high-density single output power converter, operating from a wide-range 40-V to 60-V input rail to produce a 8.0-V, 5.0-V, 3.3-V or 1.8-V rail up to 40A of load current each phase. This (...)
document-generic Schematic
REFERENCE DESIGNS Download
Power for Xilinx versal adaptive compute acceleration platform (ACAP) reference design
PMP22165 — This reference design addresses Xilinx versal adaptive compute acceleration platform (ACAP) requirements and consists of a power management integrated circuit (PMIC) for system-rails, plus a multiphase controller and power stages to support higher current processor loads.  On-board dynamic (...)
document-generic Schematic
REFERENCE DESIGNS Download
Unregulated LLC module reference design for two-stage 54-V POL in data centers
PMP22519 — This reference design is for two-stage power architecture for 54V to VCore voltage regulator module (VRM) powering CPUs, GPUs and DDR memory in 48-V rack power architecture in data centers. The First-stage is an unregulated LLC resonant converter with an integrated planar magnetic structure and (...)
document-generic Schematic
REFERENCE DESIGNS Download
Small form factor 12-Vin, 1-Vout 40-A dual-phase synchronous buck reference design
PMP21872 — This reference design is a dual-phase synchronous buck solution using TPS53622 controller with two CSD95490Q5MC power-stage ICs. It takes a 12-V input and converts it to 1-V out at 40 A; 20 A per phase.
document-generic Schematic
REFERENCE DESIGNS Download
PMBus™ voltage regulator reference design for Xilinx® Virtex Ultrascale+™ FPGAs
TIDA-050020 This reference design uses the TPS53681 multiphase controller and CSD95490Q5MC smart power stages to implement a high-performance design suitable for powering the 0.85-V, 200-A, VCCINT rail of a Xilinx™ Ultrascale+™ FPGA. The secondary output of the controller can then be used to power (...)
document-generic Schematic
REFERENCE DESIGNS Download
Cavium CN99xx Thunder X2 CPU PMBus VDD/VDD SRAM core power design
TIDA-01367 The TIDA-01367 reference design uses the TPS53679 multiphase controller and CSD95490Q5MC Smart Power Stages to implement a high-performance design suitable for powering Cavium ThunderX2® ARM Processors.

The dual outputs of the controller target a 240-A, 0.8-V core rail with a six-phase design and a (...)

document-generic Schematic
REFERENCE DESIGNS Download
PMBus Voltage Regulator Reference Design for NXP QorIQ LS2085A/88A Processors
TIDA-01512 TIDA-01512 uses the TPS53681 multiphase controller and CSD95490Q5MC Smart Power Stages to implement a high-performance design suitable for powering NXP QorIQ Communications Processors.

The dual outputs of the controller target the 60-ATDC, 1.0-V core rail with a four-phase design and a 30-ATDC, 1.2-V (...)

document-generic Schematic
REFERENCE DESIGNS Download
High Density 12Vin 0.8V 200A & 3.3V 75A POL Reference Design
PMP20489 — The TPS53679-based reference design provides a single IC for control of two multi-phase outputs with up to 6 phases on main output and up to 2 phases on channel 2; up to 7 phases in all.  Multi-phase also allows output ripple cancellation and effective higher bandwidth control for a given (...)
document-generic Schematic

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