SNAS265J June   2005  – September 2015 DAC121S101 , DAC121S101-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description continued
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC and Timing Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Resistor String
      3. 8.3.3 Output Amplifier
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Input Shift Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DSP and Microprocessor Interfacing
        1. 9.1.1.1 ADSP-2101/ADSP2103 Interfacing
          1. 9.1.1.1.1 80C51/80L51 Interface
          2. 9.1.1.1.2 68HC11 Interface
          3. 9.1.1.1.3 Microwire Interface
      2. 9.1.2 Bipolar Operation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Using References as Power Supplies
      1. 10.1.1 LM4130
      2. 10.1.2 LM4050
      3. 10.1.3 LP3985
      4. 10.1.4 LP2980
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
        1. 12.1.1.1 Specification Definitions
    2. 12.2 Related Links
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DDC Package
6-Pin SOT
Top View
DAC121S101 DAC121S101-Q1 20114901.gif
DAC121S101 (Only) DGK Package
8-Pin VSSOP
Top View
DAC121S101 DAC121S101-Q1 20114902.gif

Pin Functions

PIN I/O DESCRIPTION
NAME SOT NO. VSSOP NO.
DIN 4 7 Input Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.
GND 2 8 — Ground reference for all on-chip circuitry.
NC — 2 — No Connect. There is no internal connection to these pins.
3
SCLK 5 6 Input Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin.
SYNC 6 5 Input Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
VA 3 1 — Power supply and Reference input. Should be decoupled to GND.
VOUT 1 4 Output DAC Analog Output Voltage.