SLASEA3D December   2016  – December 2023 DAC38RF80 , DAC38RF83 , DAC38RF84 , DAC38RF85 , DAC38RF90 , DAC38RF93

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Digital Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  PLL/VCO Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  SerDes Inputs
      2. 7.3.2  SerDes Rate
      3. 7.3.3  SerDes PLL
      4. 7.3.4  SerDes Equalizer
      5. 7.3.5  JESD204B Descrambler
      6. 7.3.6  JESD204B Frame Assembly
      7. 7.3.7  SYNC Interface
      8. 7.3.8  Single or Dual Link Configuration
      9. 7.3.9  Multi-Device Synchronization
      10. 7.3.10 SYSREF Capture Circuit
      11. 7.3.11 SerDes Test Modes through Serial Programming
      12. 7.3.12 SerDes Test Modes through IEEE 1500 Programming
      13. 7.3.13 Error Counter
      14. 7.3.14 Eye Scan
      15. 7.3.15 JESD204B Pattern Test
      16. 7.3.16 Multiband DUC (multi-DUC)
        1. 7.3.16.1 Multi-DUC input
        2. 7.3.16.2 Interpolation Filters
        3. 7.3.16.3 JESD204B Modes, Interpolation and Clock phase Programming
        4. 7.3.16.4 Digital Quadrature Modulator
        5. 7.3.16.5 Low Power Coarse Resolution Mixing Modes
        6. 7.3.16.6 Inverse Sinc Filter
        7. 7.3.16.7 Summation Block for Dual DUC Modes
      17. 7.3.17 PA Protection Block
      18. 7.3.18 Gain Block
      19. 7.3.19 Output Summation
      20. 7.3.20 Output Delay
      21. 7.3.21 Polarity Inversion
      22. 7.3.22 Temperature Sensor
      23. 7.3.23 Alarm Monitoring
      24. 7.3.24 Differential Clock Inputs
      25. 7.3.25 CMOS Digital Inputs
      26. 7.3.26 DAC Fullscale Output Current
      27. 7.3.27 Current Steering DAC Architecture
      28. 7.3.28 DAC Transfer Function for DAC38RF83, 93, 85
      29. 7.3.29 DAC Transfer Function for DAC38RF80/90/84
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clocking Modes
      2. 7.4.2 PLL Bypass Mode Programming
      3. 7.4.3 Internal PLL/VCO
      4. 7.4.4 CLKOUT
      5. 7.4.5 Serial Peripheral Interface (SPI)
        1. 7.4.5.1 NORMAL (RW)
        2. 7.4.5.2 WRITE_TO_CLEAR (W0C)
        3. 7.4.5.3 Writing to Reserved Bits
    5. 7.5 Register Maps
      1. 7.5.1  Chip Reset and Configuration Register (address = 0x00) [reset = 0x5803]
      2. 7.5.2  IO Configuration Register (address = 0x01) [reset = 0x1800]
      3. 7.5.3  Lane Single Detect Alarm Mask Register (address = 0x02) [reset = 0xFFFF]
      4. 7.5.4  Clock Alarms Mask Register (address = 0x03) [reset = 0xFFFF
      5. 7.5.5  SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = 0x0000]
      6. 7.5.6  SYSREF Alignment Circuit Alarms Register (address = 0x05) [reset = variable]
      7. 7.5.7  Temperature Sensor and PLL Loop Voltage Register (address = 0x06) [reset = variable]
      8. 7.5.8  Page Set Register (address = 0x09) [reset = 0x0000]
      9. 7.5.9  SYSREF Align to r1 and r3 Count Register (address = 0x78) [reset = 0x0000]
      10. 7.5.10 SYSREF Phase Count 1 and 2 Register (address = 0x79) [reset = 0x0000]
      11. 7.5.11 SYSREF Phase Count 3 and 4 Register (address = 0x7A) [reset = 0x0000]
      12. 7.5.12 Vendor ID and Chip Version Register (address = 0x7F) [reset = 0x0009]
      13. 7.5.13 Multi-DUC Configuration (PAP, Interpolation) Register (address = 0x0A) [reset = 0x02B0]
      14. 7.5.14 Multi-DUC Configuration (Mixers) Register (address = 0x0C) [reset = 0x2402]
      15. 7.5.15 JESD FIFO Control Register (address = 0x0D)[reset = 0x8000]
      16. 7.5.16 Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF]
      17. 7.5.17 Alarm Mask 2 Register (address = 0x0F) [reset = 0xFFFF]
      18. 7.5.18 Alarm Mask 3 Register (address = 0x10) [reset = 0xFFFF]
      19. 7.5.19 Alarm Mask 4 Register (address = 0x11) [reset = 0xFFFF]
      20. 7.5.20 JESD Lane Skew Register (address = 0x12) [reset = 0x0000]
      21. 7.5.21 CMIX Configuration Register (address = 0x17) [reset = 0x0000]
      22. 7.5.22 Output Summation and Delay Register (address = 0x19) [reset = 0x0000]
      23. 7.5.23 NCO Phase Path AB Register (address = 0x1C) [reset = 0x0000]
      24. 7.5.24 NCO Phase Path CD Register (address = 0x1D) [reset = 0x0000]
      25. 7.5.25 NCO Frequency Path AB Register (address = 0x1E-0x20) [reset = 0x0000 0000 0000]
      26. 7.5.26 NCO Frequency Path CD Register (address = 0x21-0x23) [reset = 0x0000 0000 0000]
      27. 7.5.27 SYSREF Use for Clock Divider Register (address = 0x24) [reset = 0x0010]
      28. 7.5.28 Serdes Clock Control Register (address = 0x25) [reset = 0x7700]
      29. 7.5.29 Sync Source Control 1 Register (address = 0x27) [reset = 0x1144]
      30. 7.5.30 Sync Source Control 2 Register (address = 0x28) [reset = 0x0000]
      31. 7.5.31 PAP path AB Gain Attenuation Step Register (address = 0x29) [reset = 0x0000]
      32. 7.5.32 PAP path AB Wait Time Register (address = 0x2A) [reset = 0x0000]
      33. 7.5.33 PAP path CD Gain Attenuation Step Register (address = 0x2B) [reset = 0x0000]
      34. 7.5.34 PAP Path CD Wait Time Register (address = 0x2C) [reset = 0x0000]
      35. 7.5.35 PAP path AB Configuration Register (address = 0x2D) [reset = 0x0FFF]
      36. 7.5.36 PAP path CD Configuration Register (address = 0x2E) [reset = 0x0FFF]
      37. 7.5.37 DAC SPI Configuration Register (address = 0x2F) [reset = 0x0000]
      38. 7.5.38 DAC SPI Constant Register (address = 0x30) [reset = 0x0000]
      39. 7.5.39 Gain for path AB Register (address = 0x32) [reset = 0x0400]
      40. 7.5.40 Gain for path CD Register (address = 0x33) [reset = 0x0400]
      41. 7.5.41 JESD Error Counter Register (address = 0x41) [reset = 0x0000]
      42. 7.5.42 JESD ID 1 Register (address = 0x46) [reset = 0x0044]
      43. 7.5.43 JESD ID 2 Register (address = 0x47) [reset = 0x190A]
      44. 7.5.44 JESD ID 3 and Subclass Register (address = 0x48) [reset = 0x31C3]
      45. 7.5.45 JESD Lane Enable Register (address = 0x4A) [reset = 0x0003]
      46. 7.5.46 JESD RBD Buffer and Frame Octets Register (address = 0x4B) [reset = 0x1300]
      47. 7.5.47 JESD K and L Parameters Register (address = 0x4C) [reset = 0x1303]
      48. 7.5.48 JESD M and S Parameters Register (address = 0x4D) [reset = 0x0100]
      49. 7.5.49 JESD N, HD and SCR Parameters Register (address = 0x4E) [reset = 0x0F4F]
      50. 7.5.50 JESD Character Match and Other Register (address = 0x4F) [reset = 0x1CC1]
      51. 7.5.51 JESD Link Configuration Data Register (address = 0x50) [reset = 0x0000]
      52. 7.5.52 JESD Sync Request Register (address = 0x51) [reset = 0x00FF]
      53. 7.5.53 JESD Error Output Register (address = 0x52) [reset = 0x00FF]
      54. 7.5.54 JESD ILA Check 1 Register (address = 0x53) [reset = 0x0100]
      55. 7.5.55 JESD ILA Check 2 Register (address = 0x54) [reset = 0x8E60]
      56. 7.5.56 JESD SYSREF Mode Register (address = 0x5C) [reset = 0x0001]
      57. 7.5.57 JESD Crossbar Configuration 1 Register (address = 0x5F) [reset = 0x0123]
      58. 7.5.58 JESD Crossbar Configuration 2 Register (address = 0x60) [reset = 0x4567]
      59. 7.5.59 JESD Alarms for Lane 0 Register (address = 0x64) [reset = 0x0000]
      60. 7.5.60 JESD Alarms for Lane 1 Register (address = 0x65) [reset = 0x0000]
      61. 7.5.61 JESD Alarms for Lane 2 Register (address = 0x66) [reset = 0x0000]
      62. 7.5.62 JESD Alarms for Lane 3 Register (address = 0x67) [reset = 0x0000]
      63. 7.5.63 JESD Alarms for Lane 4 Register (address = 0x68) [reset = 0x0000]
      64. 7.5.64 JESD Alarms for Lane 5 Register (address = 0x69) [reset = 0x0000]
      65. 7.5.65 JESD Alarms for Lane 6 Register (address = 0x6A [reset = 0x0000]
      66. 7.5.66 JESD Alarms for Lane 7 Register (address = 0x6B) [reset = 0x0000]
      67. 7.5.67 SYSREF and PAP Alarms Register (address = 0x6C) [reset = 0x0000]
      68. 7.5.68 Clock Divider Alarms 1 Register (address = 0x6D) [reset = 0x0000]
      69. 7.5.69 Clock Configuration Register (address = 0x0A) [reset = 0xFC03]
      70. 7.5.70 Sleep Configuration Register (address = 0x0B) [reset = 0x0022]
      71. 7.5.71 Divided Output Clock Configuration Register (address = 0x0C) [reset = 0x2002]
      72. 7.5.72 DAC Fullscale Current Register (address = 0x0D) [reset = 0xF000]
      73. 7.5.73 Internal SYSREF Generator Register (address = 0x10) [reset = 0x0000]
      74. 7.5.74 Counter for Internal SYSREF Generator Register (address = 0x11) [reset = 0x0000]
      75. 7.5.75 SPI SYSREF for Internal SYSREF Generator Register (address = 0x12) [reset = 0x0000]
      76. 7.5.76 Digital Test Signals Register (address = 0x1B) [reset = 0x0000]
      77. 7.5.77 Sleep Pin Control Register (address = 0x23) [reset = 0xFFFF]
      78. 7.5.78 SYSREF Capture Circuit Control Register (address = 0x24) [reset = 0x1000]
      79. 7.5.79 Clock Input and PLL Configuration Register (address = 0x31) [reset = 0x0200]
      80. 7.5.80 PLL Configuration 1 Register (address = 0x32) [reset = 0x0308]
      81. 7.5.81 PLL Configuration 2 Register (address = 0x33) [reset = 0x4018]
      82. 7.5.82 LVDS Output Configuration Register (address = 0x34) [reset = 0x0000]
      83. 7.5.83 Fuse Farm clock divider Register (address = 0x35) [reset = 0x0018]
      84. 7.5.84 Serdes Clock Configuration Register (address = 0x3B) [reset = 0x1802]
      85. 7.5.85 Serdes PLL Configuration Register (address = 0x3C) [reset = 0x8228]
      86. 7.5.86 Serdes Configuration 1 Register (address = 0x3D) [reset = 0x0x0088]
      87. 7.5.87 Serdes Configuration 2 Register (address = 0x3E) [reset = 0x0x0909]
      88. 7.5.88 Serdes Polarity Control Register (address = 0x3F) [reset = 0x0000]
      89. 7.5.89 JESD204B SYNCB OUTPUT Register (address = 0x76) [reset = 0x0000]
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Start-up Sequence
    2. 8.2 Typical Application: Multi-band Radio Frequency Transmitter
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Calculating the JESD204B SerDes Rate
        2. 8.2.2.2 Calculating valid JESD204B SYSREF Frequency
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • AAV|144
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Register Maps

Table 7-43 Register Summary
AddressResetAcronymRegister NameSection
General Configuration Registers (PAGE_SET[2:0] = 000)
0x000x5803RESET_CONFIGChip Reset and Configuration7.5.1
0x010x1800IO_CONFIGIO Configuration7.5.2
0x020xFFFFALM_SD_MASKLane Signal Detect Alarm Mask7.5.3
0x030xFFFFALM_CLK_MASKClock Alarms Mask7.5.4
0x04variable(1)ALM_SD_DETSERDES Loss of Signal Detection Alarms7.5.5
0x05variable(1)ALM_SYSREF_DETSYSREF Alignment Circuit Alarms7.5.6
0x06variable(1)TEMP_PLLVOLTTemperature Sensor and PLL Loop Voltage7.5.7
0x07-0x080x0000ReservedReserved
0x090x0000PAGE_SETPage Set7.5.8
0x0A-0x770x0000ReservedReserved
0x780x0000SYSREF_ALIGN_RSYSERF Align to r1 and r3 Count7.5.9
0x790x0000SYSREF12_CNTSYSREF Phase Count 1 and 27.5.10
0x7A0x0000SYSREF34_CNTSYSREF Phase Count 3 and 47.5.11
0x7B-0x7E0x0000ReservedReserved
0x7FvariableVENDOR_VERVendor ID and Chip Version7.5.12
Multi-DUC Configuration Registers (PAGE_SET[0] = 1 for multi-DUC1, PAGE_SET[1] = 1 for multi-DUC2)
0x0A0x02B0MULTIDUC_CFG1Multi-DUC Configuration (PAP, Interpolation)7.5.13
0x0B0x0000ReservedReserved
0x0C0x2402MULTIDUC_CFG2Multi-DUC Configuration (Mixers)7.5.14
0x0D0x8000JESD_FIFOJESD FIFO Control7.5.15
0x0E0x00FFALM_MASK1Alarm Mask 17.5.16
0x0F0xFFFFALM_MASK2Alarm Mask 27.5.17
0x100xFFFFALM_MASK3Alarm Mask 37.5.18
0x110xFFFFALM_MASK4Alarm Mask 47.5.19
0x120x0000JESD_LN_SKEWJESD Lane Skew7.5.20
0x13-0x160x0000ReservedReserved
0x170x0000CMIXCMIX Configuration7.5.21
0x180x0000ReservedReserved
0x190x0000OUTSUMOutput Summation and Delay7.5.22
0x1A-0x1B0x0000ReservedReserved
0x1C0x0000PHASE_NCOABPhase offset for AB path NCO7.5.23
0x1D0x0000PHASE_NCOCDPhase offset for CD path NCO7.5.24
0x1E-0x200x0000FREQ_NCOABFrequency for AB path NCO7.5.25
0x21-0x230x0000FREQ_NCOCDFrequency for CD path NCO7.5.26
0x240x0010SYSREF_CLKDIVSYSREF Use for Clock Divider7.5.27
0x250x7700SERDES_CLKSerdes Clock Control7.5.28
0x260x0000ReservedReserved
0x270x1144SYNCSEL1Sync Source Selection7.5.29
0x280x0000SYNCSEL2Sync Source Selection7.5.30
0x290x0000PAP_GAIN_ABPAP path AB Gain Attenuation Step7.5.31
0x2A0x0000PAP_WAIT_ABPAP path AB Wait Time at Gain = 07.5.32
0x2B0x0000PAP_GAIN_CDPAP path CD Gain Attenuation Step7.5.33
0x2C0x0000PAP_WAIT_CDPAP path CD Wait Time at Gain = 07.5.34
0x2D0x1FFFPAP_CFG_ABPAP path AB Configuration7.5.35
0x2E0x1FFFPAP_CFG_CDPAP path CD Configuration7.5.36
0x2F0x0000SPIDAC_TEST1Configuration for DAC SPI Constant7.5.37
0x300x0000SPIDAC_TEST2DAC SPI Constant7.5.38
0x310x0000ReservedReserved
0x320x0400GAINABGain for path AB7.5.39
0x330x0400GAINCDGain for path CD7.5.40
0x34-0x400x0000ReservedReserved
0x410x0000JESD_ERR_CNTJESD Error Counter7.5.41
0x42-0x450x0000ReservedReserved
0x460x0044JESD_ID1JESD ID 17.5.42
0x470x190AJESD_ID2JESD ID 27.5.43
0x480x31C3JESD_ID3JESD ID 3 and Subclass7.5.44
0x490x0000ReservedReserved
0x4A0x0003JESD_LN_ENJESD Lane Enable7.5.45
0x4B0x1300JESD_RBD_FJESD RBD Buffer and Frame Octets7.5.46
0x4C0x1303JESD_K_LJESD K and L Parameters7.5.47
0x4D0x0100JESD_M_SJESD M and S Parameters7.5.48
0x4E0x0F4FJESD_N_HD_SCRJESD N, HD and SCR Parameters7.5.49
0x4F0x1CC1JESD_MATCHJESD Character Match and Other7.5.50
0x500x0000JESD_LINK_CFGJESD Link Configuration Data7.5.51
0x510x00FFJESD_SYNC_REQJESD Sync Request7.5.52
0x520x00FFJESD_ERR_OUTJESD Error Output7.5.53
0x530x0100JESD_ILA_CFG1JESD Configuration Value used for ILA Check7.5.54
0x540x8E60JESD_ILA_CFG2JESD Configuration Value used for ILA Check7.5.55
0x55-0x5B0x0000ReservedReserved
0x5C0x0001JESD_SYSR_MODEJESD SYSREF Mode7.5.56
0x5D-0x5E0x0000ReservedReserved
0x5F0x0123JESD_CROSSBAR1JESD Crossbar Configuration 17.5.57
0x600x4567JESD_CROSSBAR2JESD Crossbar Configuration 27.5.58
0x61-0x630x0000ReservedReserved
0x640x0000JESD_ALM_L0JESD Alarms for Lane 07.5.59
0x650x0000JESD_ ALM_L1JESD Alarms for Lane 17.5.60
0x660x0000JESD_ ALM_L2JESD Alarms for Lane 27.5.61
0x670x0000JESD_ALM_L3JESD Alarms for Lane 37.5.62
0x680x0000JESD_ALM_L4JESD Alarms for Lane 47.5.63
0x690x0000JESD_ALM_L5JESD Alarms for Lane 57.5.64
0x6A0x0000JESD_ALM_L6JESD Alarms for Lane 67.5.65
0x6B0x0000JESD_ALM_L7JESD Alarms for Lane 77.5.66
0x6C0x0000ALM_SYSREF_PAPSYSREF and PAP Alarms7.5.67
0x6D0x0000ALM_CLKDIV1Clock Divider Alarms 17.5.68
0x6E-0x770x0000ReservedReserved
Miscellaneous Configuration Registers (PAGE_SET[1:0] = 00, PAGE_SET[2] = 1)
0x0A0xFC03CLK_CONFIGClock Configuration7.5.69
0x0B0x0022SLEEP_CONFIGSleep Configuration7.5.70
0x0C0xA002CLK_OUTDivided Output Clock Configuration7.5.71
0x0D0xF000DACFSDAC Fullscale Current7.5.72
0x0E-0x0F0x0000ReservedReserved
0x100x0000LCMGENInternal sysref generator7.5.73
0x110x0000LCMGEN_DIVCounter for internal sysref generator7.5.74
0x120x0000LCMGEN_SPISYSREFSPI SYSREF for internal sysref generator7.5.75
0x13-0x1A0x0000ReservedReserved
0x1B0x0000DTESTDigital Test Signals7.5.76
0x1C-0x220x0000ReservedReserved
0x230xFFFFSLEEP_CNTLSleep Pin Control7.5.77
0x240x1000SYSR_CAPTURESYSREF Capture Circuit Control7.5.78
0x25-0x300x0000ReservedReserved
0x310x0200CLK_PLL_CFGClock Input and PLL Configuration7.5.79
0x320x0308PLL_CONFIG1PLL Configuration 17.5.80
0x330x4018PLL_CONFIG2PLL Configuration 27.5.81
0x340x0000LVDS_CONFIGLVDS Output Configuration7.5.82
0x350x0018PLL_FDIVFuse farm clock divider7.5.83
0x36-0x3A0x0000ReservedReserved
0x3B0x1802SRDS_CLK_CFGSerdes Clock Configuration7.5.84
0x3C0x8228SRDS_PLL_CFGSerdes PLL Configuration7.5.85
0x3D0x0088SRDS_CFG1Serdes Configuration 17.5.86
0x3E0x0909SRDS_CFG2Serdes Configuration 27.5.87
0x3F0x0000SRDS_POLSerdes Polarity Control7.5.88
0x40-0x750x0000ReservedReserved
0x760x0000SYNCBOUTJESD204B SYNCB Output7.5.89
(1) Reflect immediately on system condition and error condition.