SLASF08 December   2021 DAC43508 , DAC53508

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: SPI
    7. 7.7  Timing Requirements: Logic
    8. 7.8  Timing Diagrams
    9. 7.9  Typical Characteristics: Static Performance
    10. 7.10 Typical Characteristics: Dynamic Performance
    11. 7.11 Typical Characteristics: General
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Update and LDAC Functionality
        3. 8.3.1.3 CLR Functionality
        4. 8.3.1.4 Output Amplifier
      2. 8.3.2 Reference
      3. 8.3.3 Power-On Reset (POR)
      4. 8.3.4 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
    6. 8.6 Register Map
      1. 8.6.1 DEVICE_CONFIG Register (address = 01h) [reset = 00FFh]
      2. 8.6.2 STATUS_TRIGGER Register (address = 02h) [reset = 0000h]
      3. 8.6.3 BRDCAST Register (address = 03h) [reset = 0000h]
      4. 8.6.4 DACn_DATA Register (address = 08h to 0Fh) [reset = 0000h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Programmable LED Biasing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Programmable Window Comparator
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.10 Typical Characteristics: Dynamic Performance

at TA = 25°C, VDD = 5.5 V, reference = 5.5 V, and DAC outputs unloaded (unless otherwise noted)

DAC code transition from midscale – 1 to midscale,
output load: 5 kΩ || 200 pF
Figure 7-36 Glitch Impulse, Rising Edge, 1-LSB Step
DAC code transition from 102d to 922d, typical
channel shown, output load: 5 kΩ || 200 pF
Figure 7-38 Full-Scale Settling Time, Rising Edge
 
Output load: 5 kΩ || 200 pF
Figure 7-40 Power-on Glitch
DAC at midscale, reference tied to VDD,
output load: 5 kΩ || 200 pF, SCLK = 1 MHz
Figure 7-42 Clock Feedthrough
 
DAC at midscale, f = 0.1 Hz to 10 Hz
Figure 7-44 Flicker Noise
DAC code transition from midscale to midscale – 1 LSB,
output load: 5 kΩ || 200 pF
Figure 7-37 Glitch Impulse, Falling Edge, 1 LSB Step
DAC code transition from 922d to 102d, typical
channel shown, output load: 5 kΩ || 200 pF
Figure 7-39 Full-Scale Settling Time, Falling Edge
 
Output load: 5 kΩ || 200 pF
Figure 7-41 Power-off Glitch
DAC at full-scale, output load: 5 kΩ || 200 pF,
VDD = 5.25 V + 0.2 VPP, VREFIN = 4.5 V
Figure 7-43 AC Power-Supply Rejection Ratio vs Frequency
 
 
Figure 7-45 Noise Spectral Density