SLAS535F September 2007 – October 2018 DAC5652A
The data input ports of the DAC5652A accept a standard positive coding with data bits DA9 and DB9 being the most significant bits (MSB). The converter outputs support a clock rate of up to 275 MSPS. The best performance is typically achieved with a symmetric duty cycle for write and clock; however, the duty cycle may vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within their specified limits.
All digital inputs of the DAC5652A are CMOS compatible. Figure 13 and Figure 14 show schematics of the equivalent CMOS digital inputs of the DAC5652A. The pullup and pulldown circuitry is approximately equivalent to 100 kΩ. The 10-bit digital data input follows the offset positive binary coding scheme. The DAC5652A is designed to operate with a digital supply (DVDD) of 3 V to 3.6 V.