Dual-Channel, 10-Bit, 275-MSPS Digital-to-Analog Converter (DAC)


Product details


Resolution (Bits) 10 Number of DAC channels (#) 2 Interface type Parallel CMOS Sample/update rate (MSPS) 275 Features Low Power Rating Catalog Interpolation 1x Power consumption (Typ) (mW) 290 SFDR (dB) 80 Architecture Current Source Operating temperature range (C) -40 to 85 Reference type Ext, Int open-in-new Find other High-speed DACs (>10MSPS)

Package | Pins | Size

TQFP (PFB) 48 81 mm² 9 x 9 VQFN (RSL) 48 36 mm² 6 x 6 open-in-new Find other High-speed DACs (>10MSPS)


  • 10-Bit Dual Transmit DAC
  • 275 MSPS Update Rate
  • Single Supply: 3.0 V to 3.6 V
  • High Spurious-Free Dynamic Range (SFDR): 80 dBc at 5 MHz
  • High Third-Order Two-Tone Intermodulation (IMD3): 78 dBc at 15.1 MHz and 16.1 MHz
  • Independent or Single Resistor Gain Control
  • Dual or Interleaved Data
  • On-Chip 1.2-V Reference
  • Low Power: 290 mW
  • Power-Down Mode: 9 mW
  • Packages:
    • 48-Pin Thin-Quad Flat Pack (TQFP)
    • 48-Pin Very-Thin-Quad Flat No-Leads (VQFN)
open-in-new Find other High-speed DACs (>10MSPS)


The DAC5652A is a monolithic, dual-channel, 10-bit, high-speed digital-to-analog converter (DAC) with on-chip voltage reference.

Operating with update rates of up to 275 MSPS, the DAC5652A offers exceptional dynamic performance, tight-gain, and offset matching characteristics that make it suitable in either I/Q baseband or direct IF communication applications.

Each DAC has a high-impedance, differential-current output, suitable for single-ended or differential analog-output configurations. External resistors allow scaling of the full-scale output current for each DAC separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used.

The DAC5652A has two, 10-bit, parallel input ports with separate clocks and data latches. For flexibility, the DAC5652A also supports multiplexed data for each DAC on one port when operating in the interleaved mode.

The DAC5652A has been specifically designed for a differential transformer-coupled output with a 50-Ω doubly-terminated load. For a 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2-dBm output power) are supported.

The DAC5652A is available in 48-pin TQFP and 48-pin VQFN packages. The TQFP package offers pin compatibility between family members that provides 10-bit (DAC5652A), 12-bit (DAC5662), and 14-bit (DAC5672) resolution. The TQFP package is also pin compatible to the DAC2900 and AD9763 dual DACs. The device is characterized for operation over the industrial temperature range of –40°C to +85°C.

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Technical documentation

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Type Title Date
* Data sheet DAC5652A Dual, 10-Bit, 275-MSPS Digital-to-Analog Converter datasheet (Rev. F) Oct. 10, 2018
Technical article Keys to quick success using high-speed data converters Oct. 13, 2020
User guide DAC5652AEVM User's Guide May 11, 2018
Technical article Digital signal processing in RF sampling DACs – part 2 Apr. 04, 2017
Technical article Digital signal processing in RF sampling DACs - part 1 Feb. 13, 2017
Technical article Why phase noise matters in RF sampling converters Nov. 28, 2016
Application note High Speed, Digital-to-Analog Converters Basics (Rev. A) Oct. 23, 2012

Design & development

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Hardware development

document-generic User guide

The DAC5652A evaluation module (EVM) is used to evaluate the DAC5652A, which is a 10-bit, 275-MSPS digital-to-analog converter (DAC). DAC5652AEVM has a single-ended, transformer-coupled analog output to accommodate the DAC5652A full-scale output sampling range. The EVM is designed to connect (...)

  • 10-bit dual-transmit digital-to-analog converter (DAC)
  • 275-MSPS update rate
  • High spurious-free dynamic range (SFDR): 80 dBc at 5-MHz output
  • Dual or signal interleaved data
  • Small quad flatpack no-lead (QFN) 6-mm x 6-mm package

Design tools & simulation

SLAC171.ZIP (3 KB) - IBIS Model
SLAM328.ZIP (7 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
TQFP (PFB) 48 View options
VQFN (RSL) 48 View options

Ordering & quality

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