SBAS538D December   2013  – December 2021 DAC7750 , DAC8750

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: AC
    7. 7.7  Timing Requirements: Write Mode
    8. 7.8  Timing Requirements: Readback Mode
    9. 7.9  Timing Diagrams
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  DAC Architecture
      2. 8.3.2  Current Output Stage
      3. 8.3.3  Internal Reference
      4. 8.3.4  Digital Power Supply
      5. 8.3.5  DAC Clear
      6. 8.3.6  Power-On Reset
      7. 8.3.7  Alarm Detection
      8. 8.3.8  Watchdog Timer
      9. 8.3.9  Frame Error Checking
      10. 8.3.10 User Calibration
      11. 8.3.11 Programmable Slew Rate
    4. 8.4 Device Functional Modes
      1. 8.4.1 Setting Current-Output Ranges
      2. 8.4.2 Current-Setting Resistor
      3. 8.4.3 BOOST Configuration for IOUT
      4. 8.4.4 Filtering The Current Output
      5. 8.4.5 Output Current Monitoring
      6. 8.4.6 HART Interface
        1. 8.4.6.1 Implementing HART in 4-mA to 20-mA Mode
        2. 8.4.6.2 Implementing HART in All Current Output Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
        1. 8.5.1.1 SPI Shift Register
        2. 8.5.1.2 Write Operation
        3. 8.5.1.3 Read Operation
        4. 8.5.1.4 Stand-Alone Operation
        5. 8.5.1.5 Multiple Devices on the Bus
    6. 8.6 Register Maps
      1. 8.6.1 DACx750 Register Descriptions
        1. 8.6.1.1 Control Register
        2. 8.6.1.2 Configuration Register
        3. 8.6.1.3 DAC Registers
        4. 8.6.1.4 Reset Register
        5. 8.6.1.5 Status Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 HART Implementation
        1. 9.1.1.1 Using the CAP2 Pin
        2. 9.1.1.2 Using the ISET-R Pin
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

Figure 6-1 RHA Package, 40-Pin VQFN, Top View
Figure 6-2 PWP Package, 24-Pin HTSSOP, Top View
Table 6-1 Pin Functions
PIN TYPE DESCRIPTION
NAME RHA (VQFN) PWP (HTSSOP)
ALARM 2 3 Digital output Alarm pin. Open drain output. External pullup resistor required (10 kΩ). The pin goes low (active) when the ALARM condition is detected (open circuit, over temperature, timeout, and so on).
AVDD 36 24 Supply input Positive analog power supply.
BOOST 27 20 Analog output Boost pin. External transistor connection (optional).
CAP1 28 21 Analog input Connection for output filtering capacitor (optional).
CAP2 29 22 Analog input Connection for output filtering capacitor (optional).
CLR 5 6 Digital input Clear input. Logic high on this pin causes the part to enter CLEAR state. Active high.
DIN 8 9 Digital input Serial data input. Data are clocked into the 24-bit input shift register on the rising edge of the serial clock input. Schmitt-Trigger logic input.
DVDD 39 2 Supply input
or output		 Digital power supply. Can be input or output, depending on DVDD-EN pin.
DVDD-EN 23 16 Digital input Internal power-supply enable pin. Connect this pin to GND to disable the internal supply, or leave this pin unconnected to enable the internal supply. When this pin is connected to GND, an external supply must be connected to the DVDD pin.
GND 12, 13, 14, 15, 37 1, 11, 12 Supply input Ground reference point for all analog circuitry of the device.
GND 3, 4 4, 5 Supply input Ground reference point for all digital circuitry of the device.
HART-IN 24 17 Analog input Input pin for HART modulation.
IOUT 26 19 Analog output Current output pin
ISET-R 16 13 Analog input Connection pin for external precision resistor (15 kΩ). See Section 8 of this data sheet.
LATCH 6 7 Digital input Load DAC registers input. A rising edge on this pin loads the input shift register data into the DAC data and control registers and updates the DAC output.
NC 1, 10, 11, 19, 20, 21, 22, 30, 31, 32, 33, 34, 35, 38, 40 23 — No connection.
R3-SENSE 25 18 Analog output This pin is used as a monitoring feature for the output current. The voltage measured between the R3-SENSE pin and the BOOST pin is directly proportional to the output current.
REFOUT 17 14 Analog output Internal reference output. Connects to REFIN when using internal reference.
REFIN 18 15 Analog input Reference input
SCLK 7 8 Digital input Serial clock input of the SPI. Data can be transferred at rates up to 30 MHz. Schmitt-Trigger logic input.
SDO 9 10 Digital output Serial data output. Data are valid on the rising edge of SCLK.
Thermal Pad — — Supply input The thermal pad is internally connected to GND. For enhanced thermal performance, thermally connect the pad to a copper plane. The pad can be electrically connected to the same potential as the GND pin or left electrically unconnected provided a supply connection is made at the GND pin.