SLASFL3 September   2026 DAC90802

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
      1. 5.8.1 Typical Characteristics: Linearity
      2. 5.8.2 Typical Characteristics: Glitch
      3. 5.8.3 Typical Characteristics: Multiplying Mode
      4. 5.8.4 Typical Characteristics: Fast-Settling Mode
      5. 5.8.5 Typical Characteristics: AWG Mode
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converters
        1. 6.3.1.1 Reference
        2. 6.3.1.2 Output Span
          1. 6.3.1.2.1 Gain Overrange
        3. 6.3.1.3 Output Synchronization
        4. 6.3.1.4 Thermal Sensors
      2. 6.3.2 Power-On
      3. 6.3.3 Serial Data Interface
        1. 6.3.3.1 SPI Configurations
        2. 6.3.3.2 SPI Stream Mode
        3. 6.3.3.3 SPI Daisy Chain Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 AWG Mode
      2. 6.4.2 Fast Settling Mode
      3. 6.4.3 Multiplying Mode
  8. 7 Register Maps
    1. 7.1 COMMON Registers
    2. 7.2 HS_DATA Registers
    3. 7.3 HR_DATA Registers
  9. 8 Application and Implementation
    1. 8.1 Application
    2. 8.2 Design Requirements
      1. 8.2.1 Reference Signal Chain Information
        1. 8.2.1.1 DC Reference
        2. 8.2.1.2 AC Reference
      2. 8.2.2 Optimising the Self-Heating Trim to Achieve Lowest THD Across Frequencies for High Voltage Swing
      3. 8.2.3 Digital Interface
      4. 8.2.4 Grounding Recommendations
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Recommendation
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

6.3.3.2 SPI Stream Mode

Use the DAC90802 stream mode to maximize write throughput to the DAC, and avoid the repeated use of an address byte. In stream mode, the SPI supports only writes. Configuration and other registers besides DAC_DATA_CHx_X registers do not support stream mode. Table 6-4 shows the clock cycle count, and DAC update rate achievable at the highest 66MHz SCLK frequency.

Table 6-4 SPI Stream Mode Update Rates, SCLK 66MHz
Data Register Field Data Bytes Standard SPI Dual SPI Quad SPI
SDR DDR SDR DDR SDR DDR
CHx_DATA_HS 2 16 cycles
4.125MUPS 		8 cycles
8.25MUPS 		8 cycles
8.25MUPS 		4 cycles
16.5MUPS 		4 cycles
16.5MUPS 		2 cycles
33MUPS
CHx_DATA_HR 3 24 cycles
2.75MUPS 		12 cycles
5.5MUPS 		12 cycles
5.5MUPS 		6 cycles
11MUPS 		6 cycles
11MUPS 		3 cycles
22MUPS

Use SPI_CFG.SS_EN to configure how the SPI stream data is distributed to the two channels in DAC90802. To use the stream mode, begin the SDI input with the R/W bit as 0b. Use the address of the DAC_DATA_CHx_X register for the channel to receive the first data word with this header, followed by subsequent data words while holding CS low. As shown in the examples below, finish the stream write at a word boundary corresponding to the configured data width of the registers, by bringing CS high.

SPI_CFG.SS_EN = 0 is default, and enables interleaving of alternate data packets between the corresponding data registers of the two channels. The two channels automatically receive alternate data packets starting with the address provided, and the next data packet for the corresponding address on the alternate channel. Use SPI_CFG.SS_EN = 1 to use the highest throughput mode for a single DAC. The stream mode write is identical to SPI_CFG.SS_EN = 0, except the device uses every sequential data packet for the channel of the address provided, and no data packet from the stream is received by the alternate device channel. Sequential data update examples using standard, dual, and quad-SPI in SDR, and DDR modes are as shown below.

DAC90802 Standard SPI SDR Stream Mode for CHx_DATA_HR Figure 6-10 Standard SPI SDR Stream Mode for CHx_DATA_HR
DAC90802 Standard SPI SDR Stream Mode for CHx_DATA_HS Figure 6-11 Standard SPI SDR Stream Mode for CHx_DATA_HS
DAC90802 Dual SPI SDR Stream Mode for CHx_DATA_HR Figure 6-12 Dual SPI SDR Stream Mode for CHx_DATA_HR
DAC90802 Dual SPI SDR Stream Mode for CHx_DATA_HS Figure 6-13 Dual SPI SDR Stream Mode for CHx_DATA_HS
DAC90802 Quad SPI SDR Stream Mode for CHx_DATA_HR Figure 6-14 Quad SPI SDR Stream Mode for CHx_DATA_HR
DAC90802 Quad SPI SDR Stream Mode for CHx_DATA_HS Figure 6-15 Quad SPI SDR Stream Mode for CHx_DATA_HS
DAC90802 Quad SPI DDR Stream Mode for CHx_DATA_HR Figure 6-16 Quad SPI DDR Stream Mode for CHx_DATA_HR
DAC90802 Quad SPI DDR Stream Mode for CHx_DATA_HS Figure 6-17 Quad SPI DDR Stream Mode for CHx_DATA_HS