DLPS138C July   2018  – May 2022 DLP230KP

PRODUCTION DATA  

  1. Features
  2. Display Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics (1)
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Chipset Resources
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETERTEST CONDITIONS(2)MINTYPMAXUNIT
CURRENT
IDDSupply current: VDD(3) (4)VDD = 1.95 V65mA
VDD = 1.8 V53
IDDISupply current: VDDI(3) (4)VDDI = 1.95 V12mA
VDD = 1.8 V11
IOFFSETSupply current: VOFFSET(5) (6)VOFFSET = 10.5 V1.5mA
VOFFSET = 10 V1.4
IBIASSupply current: VBIAS(5) (6)VBIAS = 18.5 V0.3mA
VBIAS = 18 V0.29
IRESETSupply current: VRESET(6)VRESET = –14.5 V–1.3mA
VRESET = –14 V–1.2
POWER(7)
PDDSupply power dissipation: VDD(3) (4)VDD = 1.95 V126.75mW
VDD = 1.8 V95.4
PDDISupply power dissipation: VDDI(3) (4)VDDI = 1.95 V23.4mW
VDD = 1.8 V19.8
POFFSETSupply power dissipation: VOFFSET(5) (6)VOFFSET = 10.5 V15.75mW
VOFFSET = 10 V14
PBIASSupply power dissipation: VBIAS(5) (6)VBIAS = 18.5 V5.55mW
VBIAS = 18 V5.22
PRESETSupply power dissipation: VRESET(6)VRESET = –14.5 V18.85mW
VRESET = –14 V16.80
PTOTALSupply power dissipation: Total151.22190.3mW
LPSDR INPUT(8)
VIH(DC)DC input high voltage(9)0.7 × VDDVDD + 0.3V
VIL(DC)DC input low voltage(9)–0.30.3 × VDDV
VIH(AC)AC input high voltage(9)0.8 × VDDVDD + 0.3V
VIL(AC)AC input low voltage(9)–0.30.2 × VDDV
∆VTHysteresis ( VT+ – VT– )Figure 6-100.1 × VDD0.4 × VDDV
IILLow–level input currentVDD = 1.95 V; VI = 0 V–100nA
IIHHigh–level input currentVDD = 1.95 V; VI = 1.95 V100nA
LPSDR OUTPUT(10)
VOHDC output high voltageIOH = –2 mA0.8 × VDDV
VOLDC output low voltageIOL = 2 mA0.2 × VDDV
CAPACITANCE
CINInput capacitance LPSDRƒ = 1 MHz10pF
Input capacitance SubLVDSƒ = 1 MHz20pF
COUTOutput capacitanceƒ = 1 MHz10pF
CRESETReset group capacitanceƒ = 1 MHz; (540 × 120) micromirrors90150pF
Device electrical characteristics are over Section 6.4 unless otherwise noted.
All voltage values are with respect to the ground pins (VSS).
To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.
Supply power dissipation based on non–compressed commands and data.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
Supply power dissipation based on 3 global resets in 200 µs.
The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required.
LPSDR specifications are for pins LS_CLK and LS_WDATA.
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.
LPSDR specification is for pin LS_RDATA.