9.2.2.1 DLP5500 System Interface
Images are displayed on the DLP5500 via the DLPC200 controller and the DLPA200 driver. The DLP5500 interface consists of a 200-MHz (nominal) half-bus DDR input-only interface with LVDS signaling. The serial communications port (SCP), 125-kHz nominal, is used by the DLPC200 to read or write control data to both the DLP5500 and the DLPA200. The following listed signals support data transfer to the DLP5500 and DLPA200.
- DMD, 200 MHz
- DMD_CLK_AP, DMD_CLK_AN – DMD clock for A
- DMD_CLK_BP, DMD_CLK_BN – DMD clock for B
- DMD_DAT_AP, DMD_DAT_AN(1, 3, 5, 7, 9, 11, 13, 15) – Data bus A (odd-numbered pins are used for half-bus)
- DMD_DAT_BP, DMD_DAT_BN(1, 3, 5, 7, 9, 11, 13, 15) – Data bus B (odd-numbered pins are used for half-bus)
- DMD_SCRTL_AP, DMD_SCRTL_AN – S-control for A
- DMD_SCRTL_BP, DMD_SCRTL_BN – S-control for B
- DLPA200, 125 kHz
- SCP_DMD_RST_CLK – SCP clock
- SCP_DMD_EN – Enable DMD communication
- SCP_RST_EN – Enable DLPA200 communication
- SCP_DMD_RST_DI – Input data
- SCP_DMD_RST_DO – Output data