DLPS200B July   2020  – April 2021 DLP5530S-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.     Illumination Overfill Diagram
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Timing Requirements
    9.     Electrical and Timing Diagrams
    10. 6.8  Switching Characteristics
    11.     LPSDR and Test Load Circuit Diagrams
    12. 6.9  System Mounting Interface Loads
    13.     System Interface Loads Diagram
    14. 6.10 Physical Characteristics of the Micromirror Array
    15.     Array Physical Characteristics Diagram
    16. 6.11 Micromirror Array Optical Characteristics
    17. 6.12 Window Characteristics
    18. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sub-LVDS Data Interface
      2. 7.3.2 Low Speed Interface for Control
      3. 7.3.3 DMD Voltage Supplies
      4. 7.3.4 Asynchronous Reset
      5. 7.3.5 Temperature Sensing Diode
        1. 7.3.5.1 Temperature Sense Diode Theory
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Overview
      2. 8.2.2 Reference Design
      3. 8.2.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 DMD Handling
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FYS|149
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted
MIN NOM MAX UNIT
LPSDR
tr Rise slew rate (1) (20% to 80%) × VDD 0.25 V/ns
tf Fall slew rate (1) (80% to 20%) × VDD 0.25 V/ns
tW(H) Pulse duration LS_CLK high(3) 50% to 50% reference points 0.75 ns
tW(L) Pulse duration LS_CLK low(3) 50% to 50% reference points 0.75 ns
tsu Setup time(3) LS_WDATA valid before LS_CLK ↑ or LS_CLK ↓ 1.5 ns
th Hold time(3) LS_WDATA valid after LS_CLK ↑ or LS_CLK ↓ 1.5 ns
SubLVDS
tr Rise slew rate(2) 20% to 80% reference points 0.7 1 V/ns
tf Fall slew rate(2) 80% to 20% reference points 0.7 1 V/ns
tc Cycle time DCLK(3) 1.61 1.67 ns
tW(H) Pulse duration DCLK high(3) 50% to 50% reference points 0.75 ns
tW(L) Pulse duration DCLK low(3) 50% to 50% reference points 0.75 ns
tWINDOW Window time(3) (4) Setup time + Hold time 0.3 ns
tLVDS-ENABLE+REFGEN Power-up receiver(5) 2000 ns
(1) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-2
(2) See Figure 6-3
(3) See Figure 6-4
(4) See Figure 6-5
(5) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.