DLPS210 March 2021 DLP651NE
The DLP651NE DMD is part of a chipset that is controlled by the DLPC7540 display controller in conjunction with theTPS65145 PMIC and the DLPA100 power and motor controller. These guidelines are targeted at designing a PCB board with the DLP651NE DMD. The DMD board is a high-speed multi-layer PCB, with primarily high-speed digital logic including double data rate 3.2 Gbps and 250 Mbps differential data buses run to the DMD. TI recommends that full or mini power planes are used for VOFFSET, VRESET, and VBIAS. Solid planes are required for ground (VSS). The target impedance for the PCB is 50 Ω ±10% with exceptions listed in Table 10-1. TI recommends a 10 layer stack-up as described in Table 10-2. TI recommends manufacturing the PCB with a high quality FR-4 material.