DLPS036B September   2014  – October 2016 DLP9000


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Timing Requirements
    8. 7.8  Capacitance at Recommended Operating Conditions
    9. 7.9  Typical Characteristics
    10. 7.10 System Mounting Interface Loads
    11. 7.11 Micromirror Array Physical Characteristics
    12. 7.12 Micromirror Array Optical Characteristics
    13. 7.13 Optical and System Image Quality
    14. 7.14 Window Characteristics
    15. 7.15 Chipset Component Usage Specification
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 DLP9000
      2. 9.4.2 DLP9000X
    5. 9.5 Window Characteristics and Optics
      1. 9.5.1 Optical Interface and System Image Quality
      2. 9.5.2 Numerical Aperture and Stray Light Control
      3. 9.5.3 Pupil Match
      4. 9.5.4 Illumination Overfill
    6. 9.6 Micromirror Array Temperature Calculation
    7. 9.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 9.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 9.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 9.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 9.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Application using DLP9000
        1. Design Requirements
        2. Detailed Design Procedure
      2. 10.2.2 Typical Application Using DLP9000X
  11. 11Power Supply Requirements
    1. 11.1 DMD Power Supply Requirements
    2. 11.2 DMD Power Supply Power-Up Procedure
    3. 11.3 DMD Mirror Park Sequence Requirements
      1. 11.3.1 DLP9000
      2. 11.3.2 DLP9000X
    4. 11.4 DMD Power Supply Power-Down Procedure
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General PCB Recommendations
      2. 12.1.2 Power Planes
      3. 12.1.3 LVDS Signals
      4. 12.1.4 Critical Signals
      5. 12.1.5 Flex Connector Plating
      6. 12.1.6 Device Placement
      7. 12.1.7 Device Orientation
      8. 12.1.8 Fiducials
    2. 12.2 Layout Example
      1. 12.2.1 Board Stack and Impedance Requirements
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Handling
      2. 13.1.2 Device Nomenclature
      3. 13.1.3 Device Markings
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Thermal Characteristics
    2. 14.2 Package Thermal Resistance
    3. 14.3 Case Temperature

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device and Documentation Support

Device Support

Device Handling

All external signals on the DMD are protected from damage by electrostatic discharge, and are tested in accordance with JESD22-A114-B electrostatic discharge (ESD) sensitivity testing human body model (HBM).

Table 10. DMD ESD Protection Limits

Input 2000 V
Output 2000 V
VCC 2000 V
VCCI 2000 V
VBIAS 2000 V
All MBRST 2000 V

All CMOS devices require proper Electrostatic Discharge (ESD) handling procedures. Refer to drawing 2504641 DMD Handling Specification, for precautions to protect the DMD from ESD and to protect the DMD’s glass and electrical contacts. Refer to drawing 2504640 DMD Glass Cleaning Procedure, for correct and consistent methods for cleaning the glass of the DMD, in such a way that the anti-reflective coatings on the glass surface are not damaged.

Device Nomenclature

Figure 21 provides a legend for reading the complete device name for any DLP device.

Table 11. Package-Specific Information

DLP9000 DLPS036B_Device_Nomenclature.gif Figure 21. Device Nomenclature

Device Markings

The device marking will include both human-readable information and a 2-dimensional matrix code. The human-readable information is described in Figure 22. The 2-dimensional matrix code is an alpha-numeric character string that contains the DMD part number, Part 1 of Serial Number, and Part 2 of Serial Number. The first character of the DMD Serial Number (part 1) is the manufacturing year. The second character of the DMD Serial Number (part 1) is the manufacturing month. The last character of the DMD Serial Number (part 2) is the bias voltage bin letter.

DLP9000 DLPS036B_Device_Markings.gif Figure 22. DMD Markings

Documentation Support

Related Documentation

The following documents contain additional information related to the use of the DLP9000 family of devices:

  • DLPC900 Digital Controller Data Sheet (DLPS037)
  • DLPC900 Software Programmer's Guide (DLPU018)
  • DLPC910 Digital Controller Data Sheet (DLPS064)
  • DLPR910 Configuration PROM Data Sheet (DLPS065)

Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.


E2E is a trademark of Texas Instruments.

DLP is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

Electrostatic Discharge Caution


These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.


SLYZ022TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.