DLPS143B July   2018  – October 2020 DLPC3434

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Test Pins and General Control
    2. 5.2 Parallel Port Input
    3. 5.3 DSI Input Data and Clock
    4. 5.4 DMD Reset and Bias Control
    5. 5.5 DMD Sub-LVDS Interface
    6. 5.6 Peripheral Interface
    7. 5.7 GPIO Peripheral Interface
    8. 5.8 Clock and PLL Support
    9. 5.9 Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
    15. 6.15 Other Timing Requirements
    16. 6.16 DMD Sub-LVDS Interface Switching Characteristics
    17. 6.17 DMD Parking Switching Characteristics
    18. 6.18 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 Parallel Interface Data Transfer Format
        3. 7.3.1.3 3D Display
      2. 7.3.2 Device Startup
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Local Area Brightness Boost (LABB)
      7. 7.3.7 3D Glasses Operation
      8. 7.3.8 Test Point Support
      9. 7.3.9 DMD Interface
        1. 7.3.9.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PLL Power Layout
      2. 10.1.2 Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3 Unused Pins
      4. 10.1.4 DMD Control and Sub-LVDS Signals
      5. 10.1.5 Layer Changes
      6. 10.1.6 Stubs
      7. 10.1.7 Terminations
      8. 10.1.8 Routing Vias
      9. 10.1.9 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Video Timing Parameter Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

10.1.4 DMD Control and Sub-LVDS Signals

Table 10-4 Maximum Pin-to-Pin PCB Interconnect Recommendations
DMD BUS SIGNAL(1)(2)SIGNAL INTERCONNECT TOPOLOGYUNIT
SINGLE-BOARD SIGNAL ROUTING LENGTHMULTI-BOARD SIGNAL ROUTING LENGTH
DMD_HS_CLK_P
DMD_HS_CLK_N		6.0
(152.4)		See (3)in
(mm)
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N		6.0
(152.4)		See (3)in
(mm)
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
DMD_LS_CLK6.5
(165.1)		See (3)in
(mm)
DMD_LS_WDATA6.5
(165.1)		See (3)in
(mm)
DMD_LS_RDATA6.5
(165.1)		See (3)in
(mm)
DMD_DEN_ARSTZ7.0
(177.8)		See (3)in
(mm)
(1) Maximum signal routing length includes escape routing.
(2) Multi-board DMD routing length is more restricted due to the impact of the connector.
(3) Due to PCB variations, these recommendations cannot be defined. Any board design should SPICE simulate with the controller IBIS model (found under the Tools & Software tab of the controller web page) to ensure routing lengths do not violate signal requirements.
Table 10-5 High Speed PCB Signal Routing Matching Requirements
SIGNAL GROUP LENGTH MATCHING(1)(2)(3)
INTERFACE SIGNAL GROUP REFERENCE SIGNAL MAX MISMATCH(4) UNIT
DMD(5) DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N		 DMD_HS_CLK_P
DMD_HS_CLK_N		 ±1.0
(±25.4)		 in
(mm)
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
DMD DMD_HS_WDATA_x_P DMD_HS_WDATA_x_N ±0.025
(±0.635)		 in
(mm)
DMD DMD_HS_CLK_P DMD_HS_CLK_N ±0.025
(±0.635)		 in
(mm)
DMD DMD_LS_WDATA
DMD_LS_RDATA		 DMD_LS_CLK ±0.2
(±5.08)		 in
(mm)
DMD DMD_DEN_ARSTZ N/A N/A in
(mm)
(1) The length matching values apply to PCB routing lengths only. Internal package routing mismatch associated with the DLPC34xx controller or the DMD require no additional consideration.
(2) Training is applied to DMD HS data lines. This is why the defined matching requirements are slightly relaxed compared to the LS data lines.
(3) DMD LS signals are single ended.
(4) Mismatch variance for a signal group is always with respect to the reference signal.
(5) DMD HS data lines are differential, thus these specifications are pair-to-pair.
Table 10-6 Signal Requirements
PARAMETER REFERENCE REQUIREMENT
Source series termination DMD_LS_WDATA Required
DMD_LS_CLK Required
DMD_DEN_ARSTZ Acceptable
DMD_LS_RDATA Required
DMD_HS_WDATA_x_y Not acceptable
DMD_HS_CLK_y Not acceptable
Endpoint termination DMD_LS_WDATA Not acceptable
DMD_LS_CLK Not acceptable
DMD_DEN_ARSTZ Not acceptable
DMD_LS_RDATA Not acceptable
DMD_HS_WDATA_x_y Not acceptable
DMD_HS_CLK_y Not acceptable
PCB impedance DMD_LS_WDATA 68 Ω ±10%
DMD_LS_CLK 68 Ω ±10%
DMD_DEN_ARSTZ 68 Ω ±10%
DMD_LS_RDATA 68 Ω ±10%
DMD_HS_WDATA_x_y 100 Ω ±10%
DMD_HS_CLK_y 100 Ω ±10%
Signal type DMD_LS_WDATA SDR (single data rate) referenced to DMD_LS_DCLK
DMD_LS_CLK SDR referenced to DMD_LS_DCLK
DMD_DEN_ARSTZ SDR
DMD_LS_RDATA SDR referenced to DMD_LS_DLCK
DMD_HS_WDATA_x_y sub-LVDS
DMD_HS_CLK_y sub-LVDS