SLLSEJ7 February   2015 DP83848-HT


  1. Features
  2. Applications
  3. Description
  4. Typical System Diagram
  5. Revision History
  6. Bare Die Information
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Timing Specifications
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 100BASE-TX Transmitter
        1. Code-Group Encoding and Injection
        2. Scrambler
        3. NRZ to NRZI Encoder
        4. Binary to MLT-3 Convertor
      2. 8.3.2 100BASE-TX Receiver
        1.  Analog Front End
        2.  Digital Signal Processor
          1. Digital Adaptive Equalization and Gain Control
          2. Base Line Wander Compensation
        3.  Signal Detect
        4.  MLT-3 to NRZI Decoder
        5.  NRZI to NRZ
        6.  Serial to Parallel
        7.  Descrambler
        8.  Code-Group Alignment
        9.  4B/5B Decoder
        10. 100BASE-TX Link Integrity Monitor
        11. Bad SSD Detection
      3. 8.3.3 10BASE-T Transceiver Module
        1.  Operational Modes
          1. Half Duplex Mode
          2. Full Duplex Mode
        2.  Smart Squelch
        3.  Collision Detection and SQE
        4.  Carrier Sense
        5.  Normal Link Pulse Detection/Generation
        6.  Jabber Function
        7.  Automatic Link Polarity Detection and Correction
        8.  Transmit and Receive Filtering
        9.  Transmitter
        10. Receiver
      4. 8.3.4 Reset Operation
        1. Hardware Reset
        2. Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 MII Interface
        1. Nibble-Wide MII Data Interface
        2. Collision Detect
        3. Carrier Sense
      2. 8.4.2 Reduced MII Interface
      3. 8.4.3 10 Mb Serial Network Interface (SNI)
      4. 8.4.4 802.3u MII Serial Management Interface
        1. Serial Management Register Access
        2. Serial Management Access Protocol
        3. Serial Management Preamble Suppression
    5. 8.5 Programming
      1. 8.5.1 Auto-Negotiation
        1. Auto-Negotiation Pin Control
        2. Auto-Negotiation Register Control
        3. Auto-Negotiation Parallel Detection
        4. Auto-Negotiation Restart
        5. Enabling Auto-Negotiation via Software
        6. Auto-Negotiation Complete Time
      2. 8.5.2 Auto-MDIX
      3. 8.5.3 PHY Address
        1. MII Isolate Mode
      4. 8.5.4 LED Interface
        1. LEDs
        2. LED Direct Control
      5. 8.5.5 Half Duplex vs Full Duplex
      6. 8.5.6 Internal Loopback
      7. 8.5.7 BIST
    6. 8.6 Register Maps
      1. 8.6.1 Register Block
      2. 8.6.2 Register Definition
        1. Basic Mode Control Register (BMCR)
        2. Basic Mode Status Register (BMSR)
        3. PHY Identifier Register 1 (PHYIDR1)
        4. PHY Identifier Register 2 (PHYIDR2)
        5. Auto-Negotiation Advertisement Register (ANAR)
        6. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
        8. Auto-Negotiate Expansion Register (ANER)
        9. Auto-Negotiation Next Page Transmit Register (ANNPTR)
      3. 8.6.3 Extended Registers
        1.  PHY Status Register (PHYSTS)
        2.  MII Interrupt Control Register (MICR)
        3.  MII Interrupt Status and Miscellaneous Control Register (MISR)
        4.  False Carrier Sense Counter Register (FCSCR)
        5.  Receiver Error Counter Register (RECR)
        6.  100 Mb/s PCS Configuration and Status Register (PCSR)
        7.  RMII and Bypass Register (RBR)
        8.  LED Direct Control Register (LEDCR)
        9.  PHY Control Register (PHYCR)
        10. 10Base-T Status/Control Register (10BTSCR)
        11. CD Test and BIST Extensions Register (CDCTRL1)
        12. Energy Detect Control (EDCR)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. Clock Requirements
        2. Magnetics
      2. 9.2.2 Detailed Design Procedure
        1. TPI Network Circuit
        2. Clock In (X1) Requirements
          1. Oscillator
          2. Crystal
        3. Power Feedback Circuit
        4. Power Down and Interrupt
          1. Power-Down Control Mode
          2. Interrupt Mechanisms
        5. Energy Detect Mode
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layer Stacking
    2. 11.2 Layout Example
    3. 11.3 ESD Protection
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • KGD|0
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DP83848 is a robust, full featured, low power, 10/100 Physical Layer devices. The DP83848 features integrated sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols, which ensure compatibility and interoperability with all other standards based Ethernet products in these applications:

  • High-end peripheral devices
  • Industrial controls
  • Factor automation
  • General embedded applications

9.2 Typical Application

typapp_sllsej7.pngFigure 40. Typical Application Schematic

9.2.1 Design Requirements Clock Requirements

DP83848 supports either an external CMOS-level oscillator source or a crystal resonator device. The X1 pin is the clock input, requiring either 25 or 50 MHz depending on the MII mode used. In MII mode (or RMII master mode in some products) either a 25-MHz crystal or 25-MHz oscillator may be used. For all PHYTER family products, the use of standard RMII mode (not RMII master mode) requires the use of a 50-MHz oscillator.

Table 59. 25-MHz Crystal Oscillator Requirements

Frequency 25/50 MHz
Frequency stability ±50 ppm
Rise/fall time Max 6 ns
Jitter (short term) Max 800 ps
Jitter (long term) Max 800 ps
Load capacitance Minimum 15 pF
Symmetry 40% to 60%
Logic 0 Max 10% VDD, VDD = 3.3 V
Logic 1 Min. 90% VDD, VDD = 3.3 V Magnetics

The magnetics have a large impact on the PHY performance as well. While several components are listed, others may be compatible following the requirements listed in Table 60. TI recommends that the magnetics include both an isolation transformer and an integrated common mode choke to reduce EMI.

Table 60. Magnetics Requirements

Turn ratio 1:1, ±2%
Insertion loss –1 dB, 1 to 100 MHz
Return loss –16 dB, 1 to 30 MHz
–12 dB, 30 to 60 MHz
–10 dB, 60 to 80 MHz
Differential to common rejection ration –30 dB, 1 to 50 MHz
–20 dB, 50 to 150 MHz
Crosstalk –35 dB, 30 MHz
–30 dB, 60 MHz
Isolation 1500 Vrms

9.2.2 Detailed Design Procedure TPI Network Circuit

Figure 41 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. The transmitter and the receiver of each node are DC isolated from the network cable by 1:1 transformers. A typical network configuration provides the services of autonegotiation, Auto-MDIX, 10-Mb/s operation, and 100-Mb/s operation. Autonegotiation is a feature which automatically determines the optimal network operating speed. Auto-MDIX is a feature allowing either straight-through or cross-over cables to be used. Autonegotiation uses link pulses to determine the operating mode. Link pulses appear as differential 2.5-V signals when ideal 50-Ω balanced loading is provided. 100 Mb/s data appears as 1 V, 0 V, and –1-V differential signals, and 10-Mb/s data appears as 2.5-V and –2.5-V differential signals across ideal loading. See Figure 44, Figure 45, and Figure 46.

20205024.gifFigure 41. Typical 10/100 Mb/s Twisted Pair Interface Clock In (X1) Requirements

The DP83848 supports an external CMOS level oscillator source or a crystal resonator device. Oscillator

If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating.

Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in Table 61 and Table 62. Crystal

A 25-MHz, parallel, 20-pF load crystal resonator should be used if a crystal source is desired. Figure 42 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads.

The oscillator circuit is designed to drive a parallel resonance at cut crystal with a minimum drive level of 100 μW and a maximum of 500 μW. If a crystal is specified for a lower drive level, a current limiting resistor should be placed in series between X2 and the crystal.

As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, CL1 and CL2 should be set at 33 pF, and R1 should be set at 0 Ω.

Specification for 25 MHz crystal are listed in Table 63.

crystal_oscillator_circuit.gifFigure 42. Crystal Oscillator Circuit

Table 61. 25-MHz Oscillator Specification

Frequency 25 MHz
Frequency tolerance Operational temperature ±50 ppm
Frequency stability 1 year aging ±50 ppm
Rise/Fall time 20% to 80% 6 ns
Jitter Short term 800(1) ps
Jitter Long term 800(1) ps
Symmetry Duty cycle 40% 60%
(1) This limit is provided as a guideline for component selection and to ensure by production testing. Refer to AN-1548, PHYTER™ 100 Base-TX Reference Clock Jitter Tolerance, SNLA091 for details on jitter performance.

Table 62. 50 MHz Oscillator Specification

Frequency 50 MHz
Frequency tolerance Operational temperature ±50 ppm
Frequency stability Operational temperature ±50 ppm
Rise/Fall time 20% - 80% 6 ns
Jitter Short term 800(1) ps
Jitter Long term 800(1) ps
Symmetry Duty cycle 40% 60%
(1) This limit is provided as a guideline for component selection and to guaranteed by production testing. Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,“ for details on jitter performance.

Table 63. 25 MHz Crystal Specification

Frequency 25 MHz
Frequency tolerance Operational temperature ±50 ppm
Frequency stability 1 year aging ±50 ppm
Load capacitance 25 40 pF Power Feedback Circuit

To ensure correct operation for the DP83848, parallel caps with values of 10 μF (Tantalum) and 0.1 μF should be placed close to pin 23 (PFBOUT) of the device.

Pin 18 (PFBIN1) and pin 37 (PFBIN2) must be connected to pin 23 (PFBOUT), each pin requires a small capacitor (.1 μF). See Figure 43 for proper connections.

pwr_feeback_contn.gifFigure 43. Power Feedback Connection Power Down and Interrupt

The power down and interrupt functions are multiplexed on pin 7 of the device. By default, this pin functions as a power down input and the interrupt function is disabled. Setting bit 0 (INT_OE) of MICR (0x11h) will configure the pin as an active low interrupt output. Power-Down Control Mode

The PWR_DOWN/INT pin can be asserted low to put the device in a power down mode. This is equivalent to setting bit 11 (power down) in the basic mode control register, BMCR (0x00h). An external control signal can be used to drive the pin low, overcoming the weak internal pull-up resistor. Alternatively, the device can be configured to initialize into a power down state by use of an external pulldown resistor on the PWR_DOWN/INT pin. Since the device will still respond to management register accesses, setting the INT_OE bit in the MICR register will disable the PWR_DOWN/INT input, allowing the device to exit the power down state. Interrupt Mechanisms

The interrupt function is controlled via register access. All interrupt sources are disabled by default. Setting bit 1 (INTEN) of MICR (0x11h) will enable interrupts to be output, dependent on the interrupt mask set in the lower byte of the MISR (0x12h). The PWR_DOWN/INT pin is asynchronously asserted low when an interrupt condition occurs. The source of the interrupt can be determined by reading the upper byte of the MISR. One or more bits in the MISR will be set, denoting all currently pending interrupts. Reading of the MISR clears ALL pending interrupts.

Example: To generate an interrupt on a change of link status or on a change of energy detect power state, the steps would be:

  • Write 0003h to MICR to set INTEN and INT_OE
  • Write 0060h to MISR to set ED_INT_EN and LINK_INT_EN
  • Monitor PWR_DOWN/INT pin

When PWR_DOWN/INT pin asserts low, user would read the MISR register to see if the ED_INT or LINK_INT bits are set, i.e. which source caused the interrupt. After reading the MISR, the interrupt bits should clear and the PWR_DOWN/INT pin will deassert. Energy Detect Mode

When energy detect is enabled and there is no activity on the cable, the DP83848 will remain in a low power mode while monitoring the transmission line. Activity on the line will cause the DP83848 to go through a normal power up sequence. Regardless of cable activity, the DP83848 will occasionally wake up the transmitter to put ED pulses on the line, but will otherwise draw as little power as possible. Energy detect functionality is controlled via register energy detect control (EDCR), address 0x1Dh.

9.2.3 Application Curves

Transformers provide the functions of DC isolation from the cable, and DC biasing at the physical layer device. Isolation is necessary to meet IEEE 802.3 AC and DC isolation specifications for cabled configurations. IEEE 802.3 isolation requirements are described in section of the specification, and include the ability to sustain cable faults to 1500-V 50- or 60-Hz or 2250-Vdc voltage levels for 60 s. PHYTER product transmitters and receivers are DC biased internally, from the transformer centertap, and through 50-Ω load resistors used in typical applications.

20205001.gifFigure 44. Sample Link Pulse Waveform
20205002.gifFigure 46. Sample 10-Mb/s Waveform
20205003.gifFigure 45. Sample 100-Mb/s Waveform (MLT-3)