SNLS656D August   2020  – December 2023 DP83TD510E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Auto-Negotiation (Speed Selection)
      2. 6.3.2  Repeater Mode
      3. 6.3.3  Media Converter
      4. 6.3.4  Clock Output
      5. 6.3.5  Media Independent Interface (MII)
      6. 6.3.6  Reduced Media Independent Interface (RMII)
      7. 6.3.7  RMII Low Power 5-MHz Mode
      8. 6.3.8  RGMII Interface
      9. 6.3.9  Serial Management Interface
      10. 6.3.10 Extended Register Space Access
        1. 6.3.10.1 Read (No Post Increment) Operation
        2. 6.3.10.2 Read (Post Increment) Operation
        3. 6.3.10.3 Write (No Post Increment) Operation
        4. 6.3.10.4 Write (Post Increment) Operation
      11. 6.3.11 Loopback Modes
        1. 6.3.11.1 MII Loopback
        2. 6.3.11.2 PCS Loopback
        3. 6.3.11.3 Digital Loopback
        4. 6.3.11.4 Analog Loopback
        5. 6.3.11.5 Far-End (Reverse) Loopback
      12. 6.3.12 BIST Configurations
      13. 6.3.13 Cable Diagnostics
        1. 6.3.13.1 TDR
        2. 6.3.13.2 Fast Link Down Functionality
    4. 6.4 Device Functional Modes
      1. 6.4.1 Straps Configuration
        1. 6.4.1.1 Straps for PHY Address
    5. 6.5 Programming
    6. 6.6 MMD Register Address Map
    7. 6.7 DP83TD510E Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Termination Circuit
        1. 7.2.1.1 Termination Circuit for Intrinsic Safe Applications
        2. 7.2.1.2 Components Range for Power Coupling/Decoupling
        3. 7.2.1.3 Termination Circuit for Non-Intrinsic Safe Applications
        4. 7.2.1.4 CMC Specifications
      2. 7.2.2 Design Requirements
        1. 7.2.2.1 Clock Requirements
          1. 7.2.2.1.1 Oscillator
          2. 7.2.2.1.2 Crystal
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Signal Traces
        2. 7.4.1.2 Return Path
        3. 7.4.1.3 Metal Pour
        4. 7.4.1.4 PCB Layer Stacking
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Overview

The DP83TD510E is a physical-layer transceiver compliant to IEEE 802.3cg 10BaseT1L standards. The PHY use low noise coupled signal processing reciever architecture to offer longer cable reach along with ultra-low power consumption. The device supports both 2.4-V p2p and 1-V p2p voltage mode as defined by IEEE 802.3cg 10Base-T1L specfications. It supports mulitple MAC interface (MII, Reduced Media Independent Interface (RMII), RGMII and low power Reduced MII) for direct connection to Media Access Controller (MAC). The device also supports back-to-back RMII mode and RGMII in unmanaged mode to provide range extension and repeater functionality.

The device is designed to operate from a single 3.3-V power supply and has integrated LDO to provide the voltage rails required for internal blocks. The device has an option to feed digital power externally to achieve lowest power consumption. The device allows I/O voltage interfaces for 3.3 V, 2.5 V or 1.8 V. Automatic supply configuration within the DP83TD510E allows for any combination of VDDIO supply without the need for additional configuration settings.

The DP83TD510E is designed for use in intrinsically safe Ethernet advanced physical layer (APL) systems. Ethernet-APL is an Ethernet specification based on the IEEE 802.3.cg 10BASE-T1L standard and was developed to streamline implementation of Ethernet networking in process automation systems with intrinsic safety requirements.

A key design consideration of intrinsically safe Ethernet-APL systems – especially systems designed for use in hazardous environments with explosive potential – is the ability to reduce Ethernet PHY power levels and temperature during system failure conditions. By supporting external termination resistors, the DP83TD510E can reduce inrush current and maintain lower operating temperatures when used in long-distance process automation applications, such as field transmitters. DP83TD510E offers support for both external termination Configuration as defined in Annex A of the IEEE 802.3cg specifications. PHY is designed with innovative hybrid reciever to adjust itself for exteranl termination implementation. For non intrinsic safe applciations, DP83TD510E offers simplied external termination configuraiton with minimal external passives.

The DP83TD510E Diagonstic Tool includes TDR (Time Domain Reflectometry), ALCD (Active Link Cable Diagnostics), SQI (Signal Quality Indicator), mulitple Loopbacks and Integrated PRBS Packet Generator to ease debugging during development and detecting faulty conditions in field.