SPRS960G June   2016  – November 2019 DRA710 , DRA712 , DRA714 , DRA716 , DRA718

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  CSI2
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 ATL
      25. 4.3.25 Emulation and Debug Subsystem
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Sysboot
        2. 4.3.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.3.26.3 System Direct Memory Access (SDMA)
        4. 4.3.26.4 Interrupt Controllers (INTC)
      27. 4.3.27 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power on Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS CSI2 DC Electrical Characteristics
      6. Table 5-11 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-12 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-13 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      USBPHY DC Electrical Characteristics
      10. 5.7.2      HDMIPHY DC Electrical Characteristics
      11. 5.7.3      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-14 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics for CBD Package
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.10.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RC On-die Oscillator Clock
        2. 5.10.4.2 Output Clocks
        3. 5.10.4.3 DPLLs, DLLs
          1. 5.10.4.3.1 DPLL Characteristics
          2. 5.10.4.3.2 DLL Characteristics
          3. 5.10.4.3.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  CSI2
          1. 5.10.6.6.1 CSI-2 MIPI D-PHY
        7. 5.10.6.7  EMIF
        8. 5.10.6.8  GPMC
          1. 5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
        9. 5.10.6.9  Timers
        10. 5.10.6.10 I2C
          1. Table 5-56 Timing Requirements for I2C Input Timings
          2. Table 5-57 Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)
          3. Table 5-58 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        11. 5.10.6.11 HDQ1W
          1. 5.10.6.11.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.11.2 HDQ/1-Wire—1-Wire Mode
        12. 5.10.6.12 UART
          1. Table 5-63 Timing Requirements for UART
          2. Table 5-64 Switching Characteristics Over Recommended Operating Conditions for UART
        13. 5.10.6.13 McSPI
        14. 5.10.6.14 QSPI
        15. 5.10.6.15 McASP
          1. Table 5-71 Timing Requirements for McASP1
          2. Table 5-72 Timing Requirements for McASP2
          3. Table 5-73 Timing Requirements for McASP3/4/5/6/7/8
        16. 5.10.6.16 USB
          1. 5.10.6.16.1 USB1 DRD PHY
          2. 5.10.6.16.2 USB2 PHY
          3. 5.10.6.16.3 USB3 DRD ULPI—SDR—Slave Mode—12-pin Mode
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 DCAN
          1. Table 5-91 Timing Requirements for DCANx Receive
          2. Table 5-92 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-93 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-94 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-95 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-96 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-101 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-102 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-103 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-104 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-108 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-109 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-111 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 MLB
        21. 5.10.6.21 eMMC/SD/SDIO
          1. 5.10.6.21.1 MMC1—SD Card Interface
            1. 5.10.6.21.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.21.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.21.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.21.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.21.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.21.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.21.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.21.2 MMC2 — eMMC
            1. 5.10.6.21.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.21.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.21.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
            4. 5.10.6.21.2.4 High-speed JC64 DDR, 8-bit data
              1. Table 5-142 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
          3. 5.10.6.21.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.21.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.21.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.21.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.21.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.21.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        22. 5.10.6.22 GPIO
        23. 5.10.6.23 PRU-ICSS
          1. 5.10.6.23.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.23.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-164 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-165 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.23.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-166 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.23.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-167 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-168 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.23.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-169 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-170 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-171 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.23.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.23.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-172 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-173 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-175 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-176 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.23.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.23.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-177 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-178 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-179 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.23.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-180 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-181 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-182 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-183 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.23.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-184 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-185 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.23.5 PRU-ICSS IOSETs
          6. 5.10.6.23.6 PRU-ICSS Manual Functional Mapping
        24. 5.10.6.24 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-202 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-203 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-204 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-205 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  IVA
    6. 6.6  IPU
    7. 6.7  GPU
    8. 6.8  BB2D
    9. 6.9  PRU-ICSS
    10. 6.10 Memory Subsystem
      1. 6.10.1 EMIF
      2. 6.10.2 GPMC
      3. 6.10.3 ELM
      4. 6.10.4 OCMC
    11. 6.11 Interprocessor Communication
      1. 6.11.1 MailBox
      2. 6.11.2 Spinlock
    12. 6.12 Interrupt Controller
    13. 6.13 EDMA
    14. 6.14 Peripherals
      1. 6.14.1  VIP
      2. 6.14.2  DSS
      3. 6.14.3  Timers
        1. 6.14.3.1 General-Purpose Timers
        2. 6.14.3.2 32-kHz Synchronized Timer (COUNTER_32K)
        3. 6.14.3.3 Watchdog Timer
      4. 6.14.4  I2C
      5. 6.14.5  UART
        1. 6.14.5.1 UART Features
        2. 6.14.5.2 IrDA Features
        3. 6.14.5.3 CIR Features
      6. 6.14.6  McSPI
      7. 6.14.7  QSPI
      8. 6.14.8  McASP
      9. 6.14.9  USB
      10. 6.14.10 PCIe
      11. 6.14.11 DCAN
      12. 6.14.12 GMAC_SW
      13. 6.14.13 eMMC/SD/SDIO
      14. 6.14.14 GPIO
      15. 6.14.15 ePWM
      16. 6.14.16 eCAP
      17. 6.14.17 eQEP
    15. 6.15 On-chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 Power Regulators
        3. 7.5.2.3 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 PCIe Board Design and Layout Guidelines
        1. 7.5.5.1 PCIe Connections and Interface Compliance
          1. 7.5.5.1.1 Coupling Capacitors
          2. 7.5.5.1.2 Polarity Inversion
        2. 7.5.5.2 Non-standard PCIe connections
          1. 7.5.5.2.1 PCB Stackup Specifications
          2. 7.5.5.2.2 Routing Specifications
            1. 7.5.5.2.2.1 Impedance
            2. 7.5.5.2.2.2 Differential Coupling
            3. 7.5.5.2.2.3 Pair Length Matching
        3. 7.5.5.3 LJCB_REFN/P Connections
      6. 7.5.6 CSI2 Board Design and Routing Guidelines
        1. 7.5.6.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.6.1.1 General Guidelines
          2. 7.5.6.1.2 Length Mismatch Guidelines
            1. 7.5.6.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.6.1.3 Frequency-domain Specification Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR3 Board Design and Layout Guidelines
        1. 7.7.2.1  Board Designs
        2. 7.7.2.2  DDR3 EMIF
        3. 7.7.2.3  DDR3 Device Combinations
        4. 7.7.2.4  DDR3 Interface Schematic
          1. 7.7.2.4.1 32-Bit DDR3 Interface
          2. 7.7.2.4.2 16-Bit DDR3 Interface
        5. 7.7.2.5  Compatible JEDEC DDR3 Devices
        6. 7.7.2.6  PCB Stackup
        7. 7.7.2.7  Placement
        8. 7.7.2.8  DDR3 Keepout Region
        9. 7.7.2.9  Bulk Bypass Capacitors
        10. 7.7.2.10 High-Speed Bypass Capacitors
          1. 7.7.2.10.1 Return Current Bypass Capacitors
        11. 7.7.2.11 Net Classes
        12. 7.7.2.12 DDR3 Signal Termination
        13. 7.7.2.13 VREF_DDR Routing
        14. 7.7.2.14 VTT
        15. 7.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.2.15.1 Four DDR3 Devices
            1. 7.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.2.15.2 Two DDR3 Devices
            1. 7.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.2.15.3 One DDR3 Device
            1. 7.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.2.16 Data Topologies and Routing Definition
          1. 7.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.2.17 Routing Specification
          1. 7.7.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.2.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CBD|538
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Supply Sequences

This section describes the power-up and power-down sequence required to ensure proper device operation. The power supply names described in this section comprise a superset of a family of compatible devices. Some members of this family will not include a subset of these power supplies and their associated device modules. Refer to the Section 4.2, Pin Attributes of the Section 4, Terminal Configuration and Functions to determine which power supplies are applicable.

Figure 5-5 through Figure 5-9 and associated notes described the device Recommended Power Sequencing.

DRA710 DRA712 DRA714 DRA716 DRA718 SPRS960_ELCH_04.gifFigure 5-5 Recommended Power-Up Sequencing
  1. T0 = 0ms, T1 = 0.55ms, T2 = 1.1ms, T3 = 1.65ms, T4 = 2.2ms, T5 = 2.75ms, T6 = 3.3ms, T7 = 6.9ms, T8 ≈ 9ms. All “Tn” markers show total elapsed time from T0.
  2. Terminology:
    • VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance per Section 5.4, Recommended Operating Conditions.
    • Ramp Up = transition time from VOFF to V OPR MIN
  3. General timing diagram items:
    • Grey shaded areas show valid transition times for supplies between V OPR MIN and VOFF.
    • Dashed horizontal lines are not valid ramp times but show alternate transition times based upon common sources and clarified in associated note.
    • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power sequencer circuit performance.
  4. vdda_* rails should not be combined with vdds18v_* for best performance to avoid transient switching noise impacts on analog domains. vdda_* should not ramp-up before vdds18v_* but could ramp concurrently if design ensures final operational voltage will not be reached until after vdds18v. The preferred sequence has vdda_* following vdds18v_* to ensure circuit components and PCB design do not cause an inadvertent violation.
  5. vdds_ddr1 should not ramp-up before vdds18v_*. The preferred sequence has vdds_ddr1 following vdds18v_* to ensure circuit components and PCB design do not cause an inadvertent violation. vdds_ddr1 can ramp-up before, concurrently or after vdda_*, there are no dependencies between vdds_ddr1 and vdda_* domains.
    • For DDR2 mode of operation (1.8V), vdds_ddr1 supplies can be combined with all vdds18v_* supplies and ramped up together for simplified PDN and power sequencing.
    • If vdds_ddr1 is combined with vdds18v_ddr1 but kept separate from vdds18v on board, then this combined 1.8V DDR supply can come up together or after the vdds18v supply. The 1.8V DDR supply should never ramp up before the vdds18v.
  6. vdd should not ramp-up before vdds18v_* or vdds_ddr1 domains have reached VOPR MIN.
  7. vdd_dsp could ramp concurrently with vdd if design ensures:
    • Final vdd_dsp operational voltage will not be reached until after vdd.
    • vdd_dsp maintains a voltage level at least 150mV less than vdd during entire ramp time. The preferred sequence has vdd_dsp following vdd to ensure circuit components and PCB design do not cause an inadvertent violation.
  8. VDDA_PHY group:
    • should ramp up concurrently or after vdda33v_usb[1-2] to avoid unintended current path between vdda_pcie to vdda33v_usb1 during power sequencing.
    • could ramp up concurrently with VDDA_PLL group only if the vdda33v_usb1 power resource has an “off impedance” greater than 100Ω.
  9. vddshv[1, 3-4, 7, 9-11] domains:
    • If 1.8V I/O signaling is needed, then 1.8V must be sourced from common vdds18v supply and ramp up concurrently with vdds18v.
    • If any 3.3V I/O signaling is needed, then the desired 3.3V vddshv[1, 3-4, 7, 9-11] rails must ramp up after vdd_dsp.
  10. vdda33v_usb[1-2] domain should:
    • ramp up before or concurrently with VDDA_PHY group if USB signaling is needed and to avoid unintended current path between vdda_pcie to vdda33v_usb[1-2] during power sequencing.
    • connect to 3.3V vddshv[1, 3-4, 7, 9-11] common supply if USB signaling is not needed since USB analog power ball also supplies digital IO buffers that must be powered during operation.
  11. vddshv8 shows two ramp up options for 1.8V I/O or 3.3V I/O or SD Card operation:
    • If 1.8V I/O signaling is needed, then vddshv8 must ramp up after vdd and before or concurrently with 3.3V vddshv* rails.
    • If 3.3V I/O signaling is needed, then vddshv8 must be combined with other 3.3V vddshv* rails.
    • If SD Card operation is needed, then vddshv8 must be sourced from a dual voltage (3.3/1.8V) power source per SDIO specifications and ramp up concurrently with 3.3V vddshv* rails.
  12. porz must remain asserted low until both of the following conditions are met:
    • Minimum of 12 *P, where P = 1 / (SYS_CLK1/610), units in ns.
    • All device supply rails reach stable operational levels.
  13. Setup time: sysboot[15:0] pins must be valid 2P(12) before porz is de-asserted high.
  14. Hold time: sysboot[15:0] pins must be valid 15P(12) after porz is de-asserted high.
  15. rstoutn will be set high after global reset, due to porz, is de-asserted following an internal 2ms delay. rstoutn is only valid after vddshv3 reaches an operational level. If used as a peripheral component reset, it should be AND gated with porz to avoid possible reset glitches during power up.
DRA710 DRA712 DRA714 DRA716 DRA718 SPRS960_ELCH_05.gifFigure 5-6 Recommended Power-Down Sequencing
  1. T1 ≥ 100 µs; T2 = 500 µs; T3 = 1.0 ms; T4 = 1.5ms; V1 = 2.7 V. All "Tn" markers are intended to show total elapsed time, not interval times.
  2. Terminology:
    • VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in Section 5.4, Recommended Operating Conditions.
    • VOFF = OFF Voltage level is defined to be less than 0.6 V where any current draw has no impact to POH.
    • Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.
  3. General timing diagram items:
    • Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.
    • Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
    • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit performance.
  4. PORz must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
  5. vddshv[1, 3-4, 7, 9-11] domains supplied by 3.3 V:
    • must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 µs min after PORz is asserted low.
    • must be in first group of supplies ramping down after PORz has been asserted low for 100 µs min.
    • must not exceed vdds18v by more than 2 V during ramp down, see Figure 5-7, "vdds18v versus vddshv[1, 3-4, 7, 9-11] Discharge Relationship".
  6. vddshv[1, 3-4, 7, 9-11] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.
  7. vddshv8 supporting SD Card:
    • must be sourced from independent power resource that can provide dual voltage (3.3 / 1.8 V) operation as required to be compliant to SDIO specification
    • must be in first group of supplies to ramp down after PORz has been asserted low for 100 µs min.
    • if SDIO operation is not needed, must be grouped and ramped down with other vddshv[1, 3-4, 7, 9-11] domains as noted above.
  8. vdda33v_usb[1-2] domains:
    • can start ramping down 100 µs after low assertion of PORz
    • can ramp down concurrently or before VDDA_PHY group
  9. VDDA_PHY domain group must ramp down concurrently or after vdda33v_usb[1-2].
  10. vdd_dsp domain can ramp down before or concurrently with vdd.
  11. vdd must ramp down after or concurrently with vdd_dsp.
  12. vdds_ddr1 domain:
    • should ramp down after vdd begins ramping down.
    • If DDR2 memory is used (requiring 1.8V supply),
      • then vdds_ddr1 can be combined with vdds18v and vdds18v_ddr1 domains and sourced from a common supply. Accordingly, all domains can ramp down concurrently with vdds18v.
      • if vdds_ddr1 and vdds18v_ddr1 are combined but kept separate from vdds18v, then the combined 1.8V DDR supply can ramp down before or concurrently with vdds18v.
  13. vdda_* domains:
    • can ramp down before, concurrently or after vdds_ddr1, there is no dependency between these supplies.
    • can ramp down before or concurrently with vdds18v.
    • must satisfy the vdds18v versus vdda_* discharge relationship (see Figure 5-9) if any of the vdda_* disable point is later or discharge rate is slower than vdds18v.
  14. vdds18v domain:
    • should maintain VOPR MIN (VNOM -5% = 1.71 V) until all other supplies start to ramp down.
    • must satisfy the vdds18v versus vddshv[1, 3-4, 7, 9-11] discharge relationship (see Figure 5-7) if any of the vddshv[1, 3-4, 7, 9-11] is operating at 3.3 V.
    • must satisfy the vdds18v versus vdds_ddr1 discharge relationship ( see Figure 5-8) if vdds_ddr1 discharge rate is slower than vdds18v.

Figure 5-7 describes vddshv[1, 3-4, 7, 9-11] Supplies Falling Before vdds18v Supplies Delta.

DRA710 DRA712 DRA714 DRA716 DRA718 SPRS906_ELCH_06.gifFigure 5-7 vdds18v versus vddshv[1, 3-4, 7, 9-11] Discharge Relationship
  1. Vdelta MAX = 2V.
  2. If vddshv8 is powered by the same supply source as the other vddshv[1, 3-4, 7, 9-11] rails.

If vdds18v and vdds_ddr1 are disabled at the same time due to a loss of input power event or if vdds_ddr1 discharges more slowly than vdds18v, analysis has shown no reliability impacts when the elapsed time period beginning with vdds18v dropping below 1.0 V and ending with vdds_ddr1 dropping below 0.6 V is less than 10 ms (Figure 5-8).

DRA710 DRA712 DRA714 DRA716 DRA718 SPRS906_ELCH_07.gifFigure 5-8 vdds18v and vdds_ddr1 Discharge Relationship(1)
  1. V1 > 1.0 V; V2 < 0.6 V; T1 < 10ms.
DRA710 DRA712 DRA714 DRA716 DRA718 SPRS906_ELCH_08.gifFigure 5-9 vdds18v and vdda_* Discharge Relationship(3)
  1. vdda_* can be ≥ vdds18v, until vdds18v drops below 1.62 V.
  2. vdds18v must be ≥ vdda_*, until vdds18v reaches 0.6 V.
  3. V1 = 1.62 V; V2 < 0.6 V.

Figure 5-7 through Figure 5-10 and associated notes described the device Abrupt Power Down Sequence.

A ”loss of input power event” occurs when the system’s input power is unexpectedly removed. Normally, the recommended power-down sequence should be followed and can be accomplished within 1.5-2 ms of elapsed time. This is the typical range of elapsed time available following a loss of power event, see Section 7.3.7 for design recommendations. If sufficient elapse time is not provided, then an “abrupt” power-down sequence can be supported without impacting POH reliability if all of the following conditions are met (Figure 5-10).

DRA710 DRA712 DRA714 DRA716 DRA718 SPRS906_ELCH_09.gifFigure 5-10 Abrupt Power-Down Sequencing(1)
  1. V1 = 2.7 V; V2 = 3.3 V; V3 = 2.0 V; V4 = V5 = V6 = 0.6 V; V7 = V8 = 1.62 V; V9 = 1.3 V; V10 = 1.0 V; V11 = 0.0 V; Tdelta1 > 100 µs; Tdelta2 < 10 ms.
  2. Terminology:
    • VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in Section 5.4, Recommended Operating Conditions.
    • VOFF = OFF Voltage level is defined to be less than 0.6 V, where any current draw has no impact to POH.
    • Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.
  3. General timing diagram items:
    • Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.
    • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit performance.
  4. PORz must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
  5. vddshv[1, 3-4, 7, 9-11] domains supplied by 3.3 V:
    • must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100µs min, after PORz is asserted low.
    • must not exceed vdds18v voltage level by more than 2V during ramp down, until vdds18v drops below VOFF (0.6 V).
  6. vddshv[1, 3-4, 7, 9-11] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.
  7. vddshv8 supporting SD Card:
    • must be in first group of supplies to ramp down after PORz has been asserted low for 100 µs min.
    • must be sourced from independent power resource that can provide dual voltage (3.3 / 1.8 V) operation as required to be compliant to SDIO specification.
    • if SDIO operation is not needed, must be grouped with other vddshv[1, 3-4, 7, 9-11] domains.
  8. vdda33v_usb[1-2] domains must be in first group of supplies to ramp down after PORz has been asserted low for 100 µs min.
  9. vdd_dsp, vdd, vdds_ddr1, vdda_* domains can all start to ramp down in any order after 100 µs low assertion of PORz.
  10. vdds_ddr1 domain:
    • can remain at VOPR MIN or a level greater than vdds18v during ramp down.
    • elapsed time from vdds18v dropping below 1.0 V to vdds_ddr1 dropping below 0.6 V must not exceed 10 ms.
  11. vdda_* domains:
    • can start to ramp down before or concurrently with vdds18v.
    • must not exceed vdds18v voltage level after vdds18v drops below 1.62 V until vdds18v drops below VOFF (0.6 V).
  12. vdds18v domain should maintain a minimum level of 1.62 V (VNOM – 10%) until vdd_dsp and vdd start to ramp down.