Product details

Arm CPU 1 Arm Cortex-A15 Arm MHz (Max.) 1000 Co-processor(s) 2 Dual Arm Cortex-M4 CPU 32-bit Graphics acceleration 1 2D, 1 3D Display type 1 HDMI, 2 LCD Protocols Ethernet, ICSS, Profibus Ethernet MAC 1-Port 10/100/1000, 2-Port 1Gb switch PCIe 2 PCIe Gen 2 Hardware accelerators 1 Image Video Accelerator, 2 Viterbi Decoder, 1 Audio Tracking Logic Features Multimedia Operating system Android, Linux, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection Rating Automotive Operating temperature range (C) -40 to 125
Arm CPU 1 Arm Cortex-A15 Arm MHz (Max.) 1000 Co-processor(s) 2 Dual Arm Cortex-M4 CPU 32-bit Graphics acceleration 1 2D, 1 3D Display type 1 HDMI, 2 LCD Protocols Ethernet, ICSS, Profibus Ethernet MAC 1-Port 10/100/1000, 2-Port 1Gb switch PCIe 2 PCIe Gen 2 Hardware accelerators 1 Image Video Accelerator, 2 Viterbi Decoder, 1 Audio Tracking Logic Features Multimedia Operating system Android, Linux, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection Rating Automotive Operating temperature range (C) -40 to 125
  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
    • 2D and 3D graphics
  • Arm® Cortex®-A15 microprocessor subsystem
  • C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512KB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • DDR3/DDR3L Memory Interface (EMIF) module
    • Supports up to DDR-1333 (667 MHz)
    • Up to 2GB across single chip select
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller With DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Single-core PowerVR™ SGX544 3D GPU
  • One Video Input Port (VIP) module
    • Support for up to four multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
    • Up to two external ports
  • Sixteen 32-bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Six high-speed inter-integrated circuit (I2C) ports
  • HDQ™/1-Wire® interface
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI Interface (QSPI)
  • Media Local Bus Subsystem (MLBSS)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • High-speed USB 2.0 dual-role device
  • High-speed USB 2.0 on-the-go
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • MIPI® CSI-2 camera serial interface
  • Up to 186 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG lock
    • Secure keys
    • Secure ROM and boot
    • Customer programmable keys
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 17 mm × 17 mm, 0.65-mm pitch, 538-pin BGA (CBD)
  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
    • 2D and 3D graphics
  • Arm® Cortex®-A15 microprocessor subsystem
  • C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512KB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • DDR3/DDR3L Memory Interface (EMIF) module
    • Supports up to DDR-1333 (667 MHz)
    • Up to 2GB across single chip select
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller With DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Single-core PowerVR™ SGX544 3D GPU
  • One Video Input Port (VIP) module
    • Support for up to four multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
    • Up to two external ports
  • Sixteen 32-bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Six high-speed inter-integrated circuit (I2C) ports
  • HDQ™/1-Wire® interface
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI Interface (QSPI)
  • Media Local Bus Subsystem (MLBSS)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • High-speed USB 2.0 dual-role device
  • High-speed USB 2.0 on-the-go
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • MIPI® CSI-2 camera serial interface
  • Up to 186 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG lock
    • Secure keys
    • Secure ROM and boot
    • Customer programmable keys
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 17 mm × 17 mm, 0.65-mm pitch, 538-pin BGA (CBD)

The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Arm Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.

The device features are simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Arm Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.

The device features are simplified power supply rail mapping which enables lower cost PMIC solutions.

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Technical documentation

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Type Title Date
* Data sheet DRA71x Infotainment Applications Processor datasheet (Rev. G) 25 Nov 2019
* Errata DRA72x and DRA71x SoC for Automotive Infortainment Silicon Errata (Rev. E) 15 Feb 2021
Application note Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC 05 May 2021
Application note IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC 24 Aug 2020
White paper Jump Start Upgrading Your Digital Cluster Design with Jacinto 6 Platform (Rev. A) 17 Aug 2020
Application note AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 06 Jan 2020
Application note Integrating New Cameras With Video Input Port on DRA7xx SoCs 11 Jun 2019
User guide DRA71x and DRA72x Technical Reference Manual (Rev. D) 21 May 2019
User guide DRA71x EVM CPU board user's guide (Rev. B) 11 Mar 2019
Application note Achieving Early CAN Response on DRA7xx Devices 28 Nov 2018
Technical article Bringing the next evolution of machine learning to the edge 27 Nov 2018
Application note DRA74x_75x/DRA72x Performance (Rev. A) 31 Oct 2018
Application note Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 14 Sep 2018
Technical article How quality assurance on the Processor SDK can improve software scalability 22 Aug 2018
Application note The Implementation of YUV422 Output for SRV 02 Aug 2018
Application note MMC DLL Tuning (Rev. B) 31 Jul 2018
Application note Integrating AUTOSAR on TI SoC: Fundamentals 18 Jun 2018
Application note ECC/EDC on TDAxx (Rev. B) 13 Jun 2018
Application note Tools and Techniques to Root Case Failures in Video Capture Subsystem 12 Jun 2018
Application note Sharing VPE Between VISIONSDK and PSDKLA 04 May 2018
Application note Android Boot Optimization on DRA7xx Devices (Rev. A) 13 Feb 2018
Technical article Jacinto™ DRA automotive processors drive digital cockpit solutions 12 Jan 2018
Application note Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 30 Nov 2017
Application note Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) 27 Nov 2017
Application note Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 07 Nov 2017
Application note A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 03 Nov 2017
User guide DRA71x Cost Effective Automotive Reference Design 01 Nov 2017
Application note USB Composite Gadget Using CONFIG-FS on DRA7xx Devices 26 Sep 2017
Application note Robust Rear-View Camera (RVC) App Report 13 Sep 2017
Application note Optimization of GPU-Based Surround View on TI’s TDA2x SoC 12 Sep 2017
Application note Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 14 Aug 2017
Application note Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 12 Jul 2017
Application note Linux Boot Time Optimizations on DRA7xx Devices 31 Mar 2017
Application note Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 17 Feb 2017
Application note Early Splash Screen on DRA7x Devices 31 Jan 2017
Application note Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 15 Dec 2016
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors 21 Jul 2016
Application note Gstreamer Migration Guidelines 26 Apr 2016
User guide Jacinto6 Android Video Decoder Software Design Specification User's Guide 21 Apr 2016
User guide Jacinto6 Android Video Encoder Software Design Specification User's Guide 21 Apr 2016
Application note Flashing Binaries to DRA7xx Factory Boards Using DFU 14 Apr 2016
Application note Tools and Techniques for Audio Debugging 13 Apr 2016
Application note Debugging Tools and Techniques With IPC3.x 30 Mar 2016
Application note Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 15 Jan 2016
White paper Informational ADAS as Software Upgrade to Today’s Infotainment Systems 14 Oct 2014
Application note Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 13 Aug 2014
White paper Today’s high-end infotainment soon becoming mainstream 02 Jun 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DRA71XEVM — DRA71x Evaluation Module

Jacinto™ DRA71x evaluation module (EVM) is an evaluation platform designed to speed up development efforts and reduce time-to-market for applications such as infotainment, reconfigurable digital cluster, or integrated digital cockpit. To allow scalability and reuse across Jacinto DRA71x (...)

Software development kit (SDK)

PROCESSOR-SDK-DRA7X — Processor Software Development Kit for DRA7x Jacinto™ Processors – Linux, Android, and RTOS

Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

Operating system (OS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
From: Green Hills Software
Simulation model

DRA71x and DRA79x BSDL Model (Rev. A)

SPRM695A.ZIP (15 KB) - BSDL Model
Simulation model

DRA71x and DRA79x Thermal Model

SPRM696.ZIP (2 KB) - Thermal Model
Simulation model

DRA71x and DRA79x IBIS Model

SPRM697.ZIP (9618 KB) - IBIS Model
Calculation tool

CLOCKTREETOOL — Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
Design tool

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
Reference designs

TIDEP-01002 — Cost-optimized digital cluster automotive reference design with Jacinto™ automotive processor

The Jacinto™ automotive processor Digital Cluster Automotive Reference Design (DCARD) is a cost-optimized design for reconfigurable digital cluster systems.  DCARD is a complete and self-contained 6-layer PCB design to enable 60fps digital cluster solutions on 1920x720 resolution (...)
Package Pins Download
FCBGA (CBD) 538 View options

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