SLVSBA8G March   2012  – March 2018 DRV110

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      DRV110 Supplied by Power Line Voltage
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Keep Time
      2. 7.3.2 PWM Current Control
      3. 7.3.3 Configuring Peak and Hold Currents
      4. 7.3.4 Configuring the PWM Frequency
      5. 7.3.5 Voltage Supply and Integrated Zener Diode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Current Limiting Resistor Selection
        2. 8.2.2.2 Passive Component Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

VIN = 14 V, –40°C ≤ TA ≤ 125°C, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Standby current EN = 0, VIN = 14 V, bypass deactivated 200 250 µA
Quiescent current EN = 1, VIN = 14 V, bypass deactivated 360 570
Internally regulated supply EN = 0, IVIN = 2 mA, bypass activated 10.5 15 19 V
EN = 1, IVIN = 2 mA, bypass activated 14.5 15 15.5
GATE DRIVER
VDRV Gate drive voltage Supply voltage in regulation VIN V
IDRV_SINK Gate drive sink current VOUT = 15 V; VIN = 15 V 8 15 mA
IDRV_SOURCE Gate drive source current VOUT = GND; VIN = 15 V –15 –10 mA
fPWM PWM clock frequency OSC = GND 15 20 27 kHz
DMAX Maximum PWM duty cycle 100%
DMIN Minimum PWM duty cycle 7.5%
tD Start-up delay Delay between EN going high until gate driver starts switching, fPWM = 20 kHz 50 µs
CURRENT CONTROLLER, INTERNAL SETTINGS
IPEAK Peak current RSENSE = 1 Ω, PEAK = GND 270 300 330 mA
IHOLD Hold current RSENSE = 1 Ω, HOLD = GND 40 50 65 mA
CURRENT CONTROLLER, EXTERNAL SETTINGS
tKEEP Externally set keep time at peak current CKEEP = 1 µF 100 ms
VPEAK Voltage of internal reference to which the SENSE pin voltage is compared to for IPEAK RPEAK = 50 kΩ 900 mV
RPEAK = 200 kΩ 300
VHOLD Voltage of internal reference to which the SENSE pin voltage is compared for IHOLD RHOLD = 50 kΩ 150 mV
RHOLD = 200 kΩ 50
fPWM Externally set PWM clock frequency ROSC = 160 kΩ 25 kHz
ROSC = 200 kΩ 20
LOGIC INPUT LEVELS (EN)
VIL Input low level 1.3 V
VIH Input high level 1.65 V
REN Input pullup resistance 350 500 kΩ
Input pulldown resistance 250 kΩ
LOGIC OUTPUT LEVELS (STATUS)
VOL Output low level Pulldown activated, ISTATUS = 2 mA 0.3 V
IIL Output leakage current Pulldown deactivated, V(STATUS) = 5 V 2 µA
UNDERVOLTAGE LOCKOUT
VUVLO Undervoltage lockout threshold 4.6 V
THERMAL SHUTDOWN
TTSU Junction temperature start-up threshold 140 °C
TTSD Junction temperature shutdown threshold 160 °C