7.3.1 VCM Driver Output Stage Operation

Current in the VCM can be controlled with a linear or PWM mode output stage. Output stage is enabled in ACTIVE mode which can be controlled through VCM_CURRENT control register and the output stage mode is selected from MODE register bit PWM/LIN.

In linear mode the output PMOS is configured to a high side current source and current can be controlled from a VCM_CURRENT registers.

In PWM control the VCM is driven with a half bridge driver. With PWM control the VCM current is increased by connecting the VCM between V_BAT and GND through the high side PMOS and then released to a freewheeling mode through the sense resistor and low side NMOS. Current in the VCM is sensed with a 1-Ω sense resistor which is connected into an error amplifier input where the other input is controlled by the 10-bit DAC output. PWM mode switching frequency can be selected from 0.5 MHz up to 4 MHz through a CONTROL register. PWM or linear mode can be selected with the PWM/LIN bit in the MODE register.

7.3.2 Ringing Compensation

VCM current can be controlled via an I²C interface and VCM_CURRENT registers. Lens stack is connected to a spring which causes a dampened ringing in the lens position when current is changed. This mechanical ringing is compensated internally by generating an optimized ramp whenever the current value in the VCM_CURRENT register is changed. This enables a fast auto focus algorithm and pleasant user experience.

Ringing compensation is dependent on the VCM resonance frequency, and this can be controlled via VCM_FREQ register (07h) from 50 Hz up 150 Hz. Table 1 shows the VCM_FREQ register setting for each resonance frequency in 1-Hz steps. If more accurate resonance frequency is available, the control value can be calculated with Equation 1.

Ringing compensation is designed in a way that it can tolerate ±30% frequency variation in the VCM resonance frequency when 2/f_VCM compensation is used and ±10% variation with 1/f_VCM so only statistical data from the VCM is needed in production.

7.4.1 Modes of Operation

7.5.1 I²C Bus Operation

The I²C bus is a communications link between a controller and a series of slave terminals. The link is established using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is sourced from the controller in all cases where the serial data line is bi-directional for data communication between the controller and the slave terminals. Each device has an open drain output to transmit data on the serial data line. An external pullup resistor must be placed on the serial data line to pull the drain output high during data transmission.

The DRV201 hosts a slave I²C interface that supports data rates up to 400 kbit/s and auto-increment addressing and is compliant to I²C standard 3.

DRV201 supports four different read and two different write operations: single read from a defined location, single read from a current location, sequential read starting from a defined location, sequential read from current location, single write to a defined location, sequential write starting from a defined location. All different read and write operations are described below.

7.5.1.1 Single Write to a Defined Location

Figure 6 shows the format of a single write to a defined register. First, the master issues a start condition followed by a seven-bit I2C address. Next, the master writes a zero to conduct a write operation. Upon receiving an acknowledge from the slave, the master writes the eight-bit register number across the bus. Following a second acknowledge, DRV201 sets the I²C register to a defined value and the master writes the eight-bit data value across the bus. Upon receiving a third acknowledge, DRV201 auto increments the internal I²C register number by one and the master issues a stop condition. This action concludes the register write.

Figure 6. Single Write

7.5.1.2 Single Read from a Defined Location and Current Location

Figure 7 shows the format of a single read from a defined location. First, the master issues a start condition followed by a seven-bit I²C address. Next, the master writes a zero to conduct a write operation. Upon receiving an acknowledge from the slave, the master writes the eight-bit register number across the bus. Following a second acknowledge, DRV201 sets the internal I²C register number to a defined value. Then the master issues a repeat start condition and a seven-bit I²C address followed by a one to conduct a read operation. Upon receiving a third acknowledge, the master releases the bus to the DRV201. The DRV201 then writes the eight-bit data value from the register across the bus. The master acknowledges receiving this byte and issues a stop condition. This action concludes the register read.

Figure 7. Single Read from a Defined Location

Figure 8 shows the single read from the current location. If the read command is issued without defining the register number first, DRV201 writes out the data from the current register from the device memory.

Figure 8. Single Read from the Current Location

7.5.1.3 Sequential Read and Write

Sequential read and write allows simple and fast access to DRV201 registers. Figure 9 shows sequential read from a defined location. If the master doesn’t issue a stop condition after giving ACK, DRV201 auto increments the register number and writes the data from the next register.

Figure 9. Sequential Read from a Defined Location

Figure 10 shows the sequential write. If the master doesn’t issue a stop condition after giving ACK, DRV201 auto increments it’s register by one and the master can write to the next register.

Figure 10. Sequential Write

If read is started without writing the register value first, DRV201 writes out data from the current location. If the master doesn’t issue a stop condition after giving ACK, DRV201 auto increments the I²C register and writes out the data. This continues until the master issues a stop condition. This is shown in Figure 11.

Figure 11. Sequential Read Starting from a Current Location

7.5.2 I²C Device Address, Start and Stop Condition

Data transmission is initiated with a start bit from the controller as shown in Figure 12. The start condition is recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon reception of a start bit, the device will receive serial data on the SDA input and check for valid address and control information. SDA data is latched by DRV201 on the rising edge of the SCL line. If the appropriate device address bits are set for the device, DRV201 issues the ACK by pulling the SDA line low on the next falling edge after 8th bit is latched. SDA is kept low until the next falling edge of the SCL line.

Data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and data words. Reference Figure 13.

Figure 12. I²C Start/Stop/Acknowledge Protocol

Figure 13. I²C Data Transmission Protocol

7.6.1 Register Address Map

7.6.2 Control Register (Control) Address – 0x02h

7.6.3 VCM MSB Current Control Register (VCM_Current_MSB) Address – 0x03h

7.6.4 VCM LSB Current Control Register (VCM_Current_LSB) Address – 0x04h

7.6.5 Status Register (Status) Address – 0x05h

7.6.6 Mode Register (Mode) Address – 0x06h

7.6.7 VCM Resonance Frequency Register (VCM_FREQ) Address – 0x07h

Table 7. Bit Definitions

FIELD NAME	BIT DEFINITION
VCM_FREQ[7:0]	VCM mechanical ringing frequency for the ringing compensation can be selected with the below formula. The formula gives the VCM_FREQ[7:0] register value in decimal which should be rounded to the nearest integer.
	Equation 1.
	Default VCM mechanical ringing frequency is 76.4 Hz.
	Equation 2.