SLOS825E December 2012 – April 2018 DRV2605
This bit is the noise-gate threshold for PWM and analog inputs.
2: 4% (Default)
This bit selects mode of operation while in ERM mode. Closed-loop operation is usually desired for because of automatic overdrive and braking properties. However, many existing waveform libraries were designed for open-loop operation, therefore open-loop operation can be required for compatibility.
0: Closed Loop
1: Open Loop
This bit disables supply compensation. The DRV2605 device generally provides constant drive output over variation in the power supply input (VDD). In some systems, supply compensation can have already been implemented upstream, therefore disabling the DRV2605 supply compensation can be useful.
0: Supply compensation enabled
1: Supply compensation disabled
This bit selects the input data interpretation for RTP (Real-Time Playback) mode.
This bit selects the drive mode for the LRA algorithm. This bit determines how often the drive amplitude is updated. Updating once per cycle provides a symmetrical output signal, while updating twice per cycle provides more precise control.
0: Once per cycle
1: Twice per cycle
This bit selects the input mode for the IN/TRIG pin when MODE[2:0] = 3. In PWM input mode, the duty cycle of the input signal determines the amplitude of the waveform. In analog input mode, the amplitude of the input determines the amplitude of the waveform.
0: PWM Input
1: Analog Input
This bit selects an open-loop drive option for LRA Mode. When asserted, the playback engine drives the LRA at the selected frequency independently of the resonance frequency. In PWM input mode, the playback engine recovers the LRA commutation frequency from the PWM input, dividing the frequency by 128. Therefore the PWM input frequency must be equal to 128 times the resonant frequency of the LRA.
0: Auto-resonance mode
1: LRA open-loop mode