SLVSGS6 October   2023 DRV3901-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Power Supplies and Monitors
        1. 7.3.2.1 VDRV and VDD Power Supplies
        2. 7.3.2.2 VREG Switch
        3. 7.3.2.3 VDRV Monitor
        4. 7.3.2.4 VDD Monitor
        5. 7.3.2.5 Reset (nPOR)
        6. 7.3.2.6 Device Safety Layer
      3. 7.3.3 Output Driver
        1. 7.3.3.1 STANDBY State
        2. 7.3.3.2 ACTIVE State
        3. 7.3.3.3 Overcurrent Protection
        4. 7.3.3.4 Thermal Protection
      4. 7.3.4 Trigger (TRGx) Pins
        1. 7.3.4.1 PWM Based Trigger
        2. 7.3.4.2 Trigger Monitors
      5. 7.3.5 Deploy Parameters
        1. 7.3.5.1 Deploy Delay
      6. 7.3.6 Off-State Diagnostics
        1. 7.3.6.1 Device BIST
        2. 7.3.6.2 Weak Pull-Up Test
        3. 7.3.6.3 Weak Pull-Down Test
        4. 7.3.6.4 High-Side MOSFET RDSON Test
        5. 7.3.6.5 Low-Side MOSFET RDSON Test
        6. 7.3.6.6 IREF Resistance Monitor
        7. 7.3.6.7 VREG Voltage and Capacitance Measurement
        8. 7.3.6.8 Output Load Resistance Monitor
      7. 7.3.7 SPI Watchdog Monitor
      8. 7.3.8 nFAULT/NAD Pin
      9. 7.3.9 Fault Tables
        1. 7.3.9.1 General Device Faults
        2. 7.3.9.2 Off-State Diagnostic Faults
        3. 7.3.9.3 Deployment Faults
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 Addressable SPI
      3. 7.5.3 SPI Error Indicators
      4. 7.5.4 SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 STATUS Registers
      2. 7.6.2 MEAS Registers
      3. 7.6.3 CONFIG Registers
      4. 7.6.4 CMD Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plots
      4. 8.2.4 Initialization Setup
        1. 8.2.4.1 Device Initialization - NAD
        2. 8.2.4.2 Device Initialization - Configuration
        3. 8.2.4.3 System Initialization
          1. 8.2.4.3.1 Trigger PWM Pattern Check
          2. 8.2.4.3.2 Device Timing Check
          3. 8.2.4.3.3 nFAULT Signalling Check
          4. 8.2.4.3.4 Secondary Logic Check
          5. 8.2.4.3.5 Off-State Diagnostics - Initial Check
        4. 8.2.4.4 Off-State Diagnostics - Periodic Check
        5. 8.2.4.5 Deployment
          1. 8.2.4.5.1 Targeted Device Deployment
          2. 8.2.4.5.2 Broadcast Deployment
          3. 8.2.4.5.3 Off-State Diagnostics - Post Deployment
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
  11. 10Mechanical Packaging and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.6.4 High-Side MOSFET RDSON Test

There are two parts to this test. First, with the driver disabled (Hi-Z), this test forces a pull up current (IREF_PC_HSRDSON) on OUTH until the output has reached a voltage close to VDRV pre-charge (VREF_PC_HSRDSON). After this, only the high-side (HS) MOSFET switch is turned on with an user configured pull down current (IREF_HSRDSON) on OUTH and the drain to source voltage of the HS MOSFET switch is compared to an internal reference (VREF_HSRDSON). The test has a user configured time out (tHSRDSON). The HS MOSFET is protected by IOCP_HS_RDSON to ensure the MOSFET is switched off in the case of a short-circuit on the output.

A test failure results in abortion of off-state diagnostics and is reported as OFF_DIAG_STAT = 0xB in the STATUS registers with additional information in the OFF_DIAG_STAT_MISC register to differentiate between a pre-charge time out or RDSON failure.

While the user can skip this test with register OFF_DIAG_HS_RDSON_DIS = 0x1, it is recommended to skip both the LS and HS MOSFET switch tests together, and not skip only the LS or HS test.

DRV3901-Q1 HS MOSFET RDSON Test Diagram Figure 7-14 HS MOSFET RDSON Test Diagram