SLVSGS6 October   2023  – July 2026 DRV3901-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 ESD Ratings
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 External Components
      2. 6.3.2 Power Supplies and Monitors
        1. 6.3.2.1 VDRV and VDD Power Supplies
        2. 6.3.2.2 VREG Switch
        3. 6.3.2.3 VDRV Monitor
        4. 6.3.2.4 VDD Monitor
        5. 6.3.2.5 Reset (nPOR)
        6. 6.3.2.6 Device Safety Layer
      3. 6.3.3 Output Driver
        1. 6.3.3.1 STANDBY State
        2. 6.3.3.2 ACTIVE State
        3. 6.3.3.3 Overcurrent Protection
        4. 6.3.3.4 Thermal Protection
      4. 6.3.4 Trigger (TRGx) Pins
        1. 6.3.4.1 PWM Based Trigger
        2. 6.3.4.2 Trigger Monitors
      5. 6.3.5 Deploy Parameters
        1. 6.3.5.1 Deploy Delay
      6. 6.3.6 Off-State Diagnostics
        1. 6.3.6.1 Device BIST
        2. 6.3.6.2 Weak Pull-Up Test
        3. 6.3.6.3 Weak Pull-Down Test
        4. 6.3.6.4 High-Side MOSFET RDSON Test
        5. 6.3.6.5 Low-Side MOSFET RDSON Test
        6. 6.3.6.6 IREF Resistance Monitor
        7. 6.3.6.7 VREG Voltage and Capacitance Measurement
        8. 6.3.6.8 Output Load Resistance Monitor
      7. 6.3.7 SPI Watchdog Monitor
      8. 6.3.8 nFAULT/NAD Pin
      9. 6.3.9 Fault Tables
        1. 6.3.9.1 General Device Faults
        2. 6.3.9.2 Off-State Diagnostic Faults
        3. 6.3.9.3 Deployment Faults
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 SPI Interface
      2. 6.5.2 Addressable SPI
      3. 6.5.3 SPI Error Indicators
      4. 6.5.4 SPI Format
  8. 7 Register Maps
    1. 7.1 STATUS Registers
    2. 7.2 MEAS Registers
    3. 7.3 CONFIG Registers
    4. 7.4 CMD Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plots
      4. 8.2.4 Initialization Setup
        1. 8.2.4.1 Device Initialization - NAD
        2. 8.2.4.2 Device Initialization - Configuration
        3. 8.2.4.3 System Initialization
          1. 8.2.4.3.1 Trigger PWM Pattern Check
          2. 8.2.4.3.2 nFAULT Signalling Check
          3. 8.2.4.3.3 Device Timing Check
          4. 8.2.4.3.4 Secondary Logic Check
          5. 8.2.4.3.5 Off-State Diagnostics - Initial Check
        4. 8.2.4.4 Off-State Diagnostics - Periodic Check
        5. 8.2.4.5 Deployment
          1. 8.2.4.5.1 Targeted Device Deployment
          2. 8.2.4.5.2 Broadcast Deployment
          3. 8.2.4.5.3 Off-State Diagnostics - Post Deployment
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
  11. 10Revision History
  12. 11Mechanical Packaging and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.6 Off-State Diagnostics

From the STANDBY state, the device can be commanded to perform off-state diagnostics with a valid SPI command. The diagnostics include a series of sequenced, self-timed tests that check the availability of the deployment function without creating a risk of inadvertent deployment.

Failure in any of the first six tests results in aborting the off-state diagnostics at the instant of the failure. Off-state diagnostics function is not available in case of VDRV undervoltage, VDRV overvoltage warning, or over temperature warning. The results are captured in the STATUS registers, OFF_DIAG_STAT and OFF_DIAG_SUM.

At any time during off-state diagnostics, the device can accept a valid pin TRG or SPI command to deploy. At this point, the device aborts the diagnostics instantly in controlled manner and transition to ACTIVE state for deployment. The deployment delay parameters tDLY0 and tDLY1 times are still maintained.

The sequence of tests and their objective is as follows:

  1. Device BIST: Device BIST to qualify the monitors.
  2. Weak Pull-Up Test: Detect an impedance to ground.
  3. Weak Pull-Down Test: Detect an impedance to supply or an open loop.
  4. HS RDSON Test (disabled by default): Device high-side MOSFET check
  5. LS RDSON Test (disabled by default): Device low-side MOSFET check.
  6. IREF Resistance Monitor: Resistance measurement check for external IREF pin resistor.
  7. VREG Voltage and Capacitance Measurement: Measures the voltage on VREG (BIST included) with respect to PVDD and reports the discharge rate of the capacitor on VREG with a controlled current sink to estimate the capacitance on the pin.
  8. Load Resistance Monitor: Check the resistance of the output squib load. (typically 2 Ω).

The sequence of the tests cannot be changed, but individual tests can be disabled through the CONFIG registers.

DRV3901-Q1 Off-State Diagnostic SequenceFigure 6-11 Off-State Diagnostic Sequence

During device operation, the following 3 combinations are recommended to conduct the off-state diagnostics:

  1. Startup check: All tests to validate the health of the device, load, and qualify the monitors.
  2. Periodic check: Weak pull up, weak pull down, VREG voltage & capacitance measurements, and load resistance monitor to validate the availability of the deployment function.
  3. Post deployment check: Load resistance monitor only to validate that initiator has been deployed.