SLVSHD9 March   2025 DRV8001-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RHA Package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-Side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Drivers - Parallel Outputs
          2. 7.4.2.1.2 High-side Driver PWM Generator
            1. 7.4.2.1.2.1 Constant Current Mode
            2. 7.4.2.1.2.2 OUT7 HS ITRIP Behavior
            3. 7.4.2.1.2.3 High-side Drivers - Parallel Outputs
          3. 7.4.2.1.3 High-side Driver Protection Circuits
            1. 7.4.2.1.3.1 High-side Drivers Internal Diode
            2. 7.4.2.1.3.2 High-side Driver Overcurrent Protection
            3. 7.4.2.1.3.3 High-side Driver Open Load Detection
      3. 7.4.3 Electrochromic Glass Driver
        1. 7.4.3.1 Electrochromic Driver Control
        2. 7.4.3.2 Electrochromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 Half-Bridge ITRIP Regulation
        3. 7.4.4.3 Half-bridge Protection and Diagnostics
          1. 7.4.4.3.1 Half-Bridge Off-State Diagnostics (OLP)
          2. 7.4.4.3.2 Half-Bridge Active Open Load Detection (OLA)
          3. 7.4.4.3.3 Half-Bridge Overcurrent Protection
      5. 7.4.5 Sense Output (IPROPI)
      6. 7.4.6 Protection Circuits
        1. 7.4.6.1 Fault Reset (CLR_FLT)
        2. 7.4.6.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.6.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.6.4 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        5. 7.4.6.5 Thermal Clusters
        6. 7.4.6.6 Watchdog Timer
        7. 7.4.6.7 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8001-Q1 Register Map
    1. 8.1 DRV8000-Q1_STATUS Registers
    2. 8.2 DRV8000-Q1_CNFG Registers
    3. 8.3 DRV8000-Q1_CTRL Registers
    4. 8.4 DRV8001-Q1_STATUS Registers
    5. 8.5 DRV8001-Q1_CNFG Registers
    6. 8.6 DRV8001-Q1_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
    3. 9.3 Initialization Setup
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance Sizing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Refer to the PDF data sheet for device specific package drawings

7.5.2 SPI Format

The SDI input data word is 24 bits long and consists of the following format:

  • MSB bit indicates frame type (bit B23 = 0 for standard frame)
  • 1 read or write bit, W (bit B22, write = 0, read = 1)
  • 6 address bits, A (bits B21 through B16)
  • 16 data bits, D (bits B15 through B0). For a read operation, these bits are typically set to null values, while for a write operation, these bits have the data value for the addressed register.

Table 7-40 SDI Input Data Word Format
R/W Address Data
Bit B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data 0 W0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

The SDO output data word is 24 bits long and the first 8 bits makes up the IC status register. The report word is the content of the register being accessed.

For a write command (W0 = 0), the response word consists of the fault status indication bits followed by the existing data in the register being written to.

For a read command (W0 = 1), the response word consists of the fault status indications bits followed by the data currently in the register being read.

Table 7-41 SDO Output Data Word Format
IC Status Report
Bit B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
Data 1 1 FAULT WARN OV_UV DRV OTSD SPI_ERR D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0

  • FAULT - 'OR' of any device fault (global or driver)
  • WARN - 'OR' of any device warnings
  • OV_UV - 'OR' of PVDD overvoltage and undervoltage status
  • DRV - 'OR' of any driver fault
  • OTSD - Set when over temperature shutdown occurs
  • SPI_ERR - Set when incorrect number of SCLKs received