The device half-bridges have optional fixed-frequency load current regulation called ITRIP. This is done by comparing the active output current against configured current thresholds determined by OUTX_ITRIP_LVL. OUT1-2 has two possible ITRIP current thresholds, and OUT3-6 also have three current threshold options. ITRIP thresholds, enables, and timing settings are set individually for each half-bridge in the HB_ITRIP_CONFIG, HB_ITRIP_FREQ and HB_ITRIP_DG.

As this device has multiple integrated drivers which are enabled at any given time, there is freewheeling configuration intended to reduce power dissipation during ITRIP half-bridge regulation. Power dissipation is lower with synchronous rectification (MOSFETs) compared with asynchronous rectification (diodes). The half-bridge freewheeling is configurable between non- and synchronous rectification (active and passive freewheeling). The freewheeling settings are shared between half-bridge pairs. The synchronous rectification for half-bridges during ITRIP regulation is enabled by setting bits NSR_OUTX_DIS in configuration register HB_OUT_CNFG1.

ITRIP detection is done on both high- and low-side MOSFETs of each half-bridge. ITRIP is dynamically blanked by internal overcurrent protection circuitry.

The configurable ITRIP timing parameters are frequency and deglitch. The tables below summarize the ITRIP configuration options.

ITRIP regulation follows these steps:

• The low- or high-side of a half-bridge is enabled. The first ITRIP clock edge occurs when half-bridge enabled.
• If ITRIP limit is exceeded on either low- or high-side, the device waits for longer than deglitch time t_{DG_ITRIP_HB}.
• If ITRIP limit is still exceeded after the deglitch time, then either the half-bridge enters the Hi-Z or turns on the opposite MOSFET for the remainder of the ITRIP cycle, depending on NSR_OUTX_DIS bit setting. ITRIP status bit is set, and the regulation loop restarts.
• If NSR_OUTX_DIS = 1b (synchronous rectification enabled), the current through the enabled MOSFET is monitored for current reversal. If current reversal is detected, the half-bridge output is Hi-Z for the remainder of the ITRIP cycle.

The synchronous rectification or freewheeling feature is enabled by setting bits NSR_OUTX_DIS in configuration register HB_OUT_CNFG1. When NSR_OUTX_DIS = 0b, if ITRIP occurs on either MOSFET, the half-bridge goes Hi-Z. If NSR_OUTX_DIS = 1b, if ITRIP occurs on either MOSFET, the opposite MOSFET is enabled.

For example, NSR_OUTX_DIS = 1b and OUTX_CNFG = 100b or 010b. If the PWM input sets HS MOSFET ON, and ITRIP is reached on HS MOSFET, the LS MOSFET turns on for the remainder of the ITRIP cycle. The HS MOSFET is turned ON at the end of the cycle. If the PWM input changes within the ITRIP period, the ITRIP counter is reset and ITRIP regulation is active while the LS MOSFET is ON.

If synchronous rectification is enabled and MOSFET turns on when ITRIP occurs, current is monitored for a current reversal, or zero-crossing detection. There is zero-crossing detection on both high-side and low-side MOSFETs. If the detected load current reaches 0A during ITRIP regulation for longer than the deglitch time, then the half-bridge output goes Hi-Z for the remainder of the ITRIP cycle. The zero-crossing deglitch time is the same ITRIP deglitch time.

The diagram below shows the ITRIP behavior for a half-bridge:

The ITRIP setting can be changed at any time when SPI communication is available by writing to the OUTX_ITRIP_LVL bits. The change is immediately reflected in device behavior.

If a half-bridge is configured for PWM control and ITRIP, when ITRIP is reached, the behavior is the same as for SPI register control, but the input now comes from the configured PWM pin.