SLOS842A September   2013  – June 2015 DRV8301-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Buck Converter Characteristics
    7. 6.7  Current Shunt Amplifier Characteristics
    8. 6.8  Gate Timing and Protection Characteristics
    9. 6.9  SPI Timing Requirements (Slave Mode Only)
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Function Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three-Phase Gate Driver
      2. 7.3.2 Current Shunt Amplifiers
      3. 7.3.3 Buck Converter
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Overcurrent Protection and Reporting (OCP)
        2. 7.3.4.2 Undervoltage Protection (PVDD_UV and GVDD_UV)
        3. 7.3.4.3 Overvoltage Protection (GVDD_OV)
        4. 7.3.4.4 Overtemperature Protection
        5. 7.3.4.5 Fault and Protection Handling
      5. 7.3.5 Start-up and Shutdown Sequence Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 EN_GATE
      2. 7.4.2 DTC
      3. 7.4.3 VDD_SPI
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 SPI
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 Read / Write Bit
      2. 7.6.2 Address Bits
      3. 7.6.3 SPI Data Bits
        1. 7.6.3.1 Status Registers
        2. 7.6.3.2 Control Registers
        3. 7.6.3.3 Overcurrent Adjustment
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Gate Driver Start-up Issue Errata
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Drive Average Current Load
        2. 8.2.2.2 Overcurrent Protection Setup
        3. 8.2.2.3 Sense Amplifier Setup
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The DRV8301-Q1 is a 6-V to 60-V gate driver IC for three-phase motor drive applications. This device reduces external component count by integrating three half-bridge drivers, two current shunt amplifiers, and a switching buck converter. The DRV8301-Q1 provides overcurrent, overtemperature, and undervoltage protection. Fault conditions are indicated through the nFAULT and nOCTW pins in addition to the SPI registers.

Adjustable dead time control and peak gate drive current allows for finely tuning the switching of the external MOSFETs. Internal hand-shaking is used to prevent flow of current.

VDS sensing of the external MOSFETs allows for the DRV8301-Q1 to detect overcurrent conditions and respond appropriately. Individual MOSFET overcurrent conditions are reported through the SPI status registers.

The highly configurable buck converter can support a wide range of output options. This allows the DRV8301-Q1 to provide a power supply rail for the controller and lower voltage components.

7.2 Function Block Diagram

DRV8301-Q1 fbd_slos842.gif

7.3 Feature Description

7.3.1 Three-Phase Gate Driver

The half-bridge drivers use a bootstrap configuration with a trickle charge pump to support 100% duty cycle operation. Each half-bridge is configured to drive two N-channel MOSFETs, one for the high-side and one for the low-side. The half-bridge drivers can be used in combination to drive a 3-phase motor or separately to drive various other loads.

The peak gate drive current and internal dead times are adjustable to accommodate a variety of external MOSFETs and applications. The peak gate drive current is set through a register setting and the dead time is adjusted with an external resistor on the DTC pin. Shorting the DTC pin to ground will provide the minimum dead time (50 ns). There is an internal hand shake between the high side and low side MOSFETs during switching transitions to prevent current shoot through.

The three-phase gate driver can provide up to 30 mA of average gate drive current. This will support switching frequencies up to 200 kHz when the MOSFET Qg = 25 nC.

Each MOSFET gate driver has a VDS sensing circuit for overcurrent protection. The sense circuit measures the voltage from the drain to the source of the external MOSFETs while the MOSFET is enabled. This voltage is compared against the programmed trip point to determine if an overcurrent event has occurred. The high-side sense is between the PVDD1 and SH_X pins. The low-side sense is between the SH_X and SL_X pins. Ensuring a differential, low impedance connection to the external MOSFETs for these lines will help provide accurate VDS sensing.

The DRV8301-Q1 allows for both 6-PWM and 3-PWM control through a register setting.

Table 1. 6-PWM Mode

INL_X INH_X GL_X GH_X
0 0 L L
0 1 L H
1 0 H L
1 1 L L

Table 2. 3-PWM Mode

INL_X INH_X GL_X GH_X
X 0 H L
X 1 L H

7.3.2 Current Shunt Amplifiers

The DRV8301-Q1 includes two high-performance current shunt amplifiers to accurate low-side, inline current measurement.

The current shunt amplifiers have four programmable GAIN settings through the SPI registers. These are 10, 20, 40, and 80 V/V.

The current shunt amplifiers provide output offset up to 3 V to support bidirectional current sensing. The offset is set to half the voltage on the reference pin (REF).

To minimize DC offset and drift overtemperature, a calibration method is provided through either the DC_CAL pin or SPI register. When DC calibration is enabled, the device will short the input of the current shunt amplifier and disconnect the load. DC calibration can be done at any time, even during MOSFET switching, because the load is disconnected. For the best results, perform the DC calibration during the switching OFF period, when no load is present, to reduce the potential noise impact to the amplifier.

The output of the current shunt amplifier can be calculated as:

Equation 1. DRV8301-Q1 EQ1_vo_los719.gif

where

  • VREF is the reference voltage (REF pin)
  • G is the gain of the amplifier (10, 20, 40, or 80 V/V)
  • SNX and SPX are the inputs of channel x. SPX should connect to the ground side of the sense resistor for the best common-mode rejection.

Figure 6 shows the current shunt amplifier simplified block diagram.

DRV8301-Q1 shunt_bd_los719.gifFigure 6. Current Shunt Amplifier Simplified Block Diagram

7.3.3 Buck Converter

The DRV8301-Q1 uses an integrated TPS54160 1.5 A, 60 V, step-down DC-DC converter. Although integrated in the same device, the buck converter is designed completely independent of the rest of the gate driver circuitry. Because the buck converter will support external MCU or other external power need, the independency of buck operation is very critical for a reliable system; this will give the buck converter minimum impact from gate driver operations. Some examples are: when gate driver shuts down due to any failure, buck will still operate unless the fault is coming from buck itself. The buck keeps operating at much lower PVDD of 3.5 V, this will assure the system to have a smooth power-up and power-down sequence when gate driver is not able to operate due to a low PVDD.

For proper selection of the buck converter external components, see TPS54160 1.5-A, 60-V, Step-Down DC/DC Converter with Eco-mode™ (SLVSB56).

The buck has an integrated high-side N-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design.

The wide switching frequency of 300 kHz to 2200 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT_CLK pin. The device has an internal phase lock loop (PLL) on the RT_CLK pin that is used to synchronize the power switch turnon to a falling edge of an external system clock.

The buck converter has a default start-up voltage of approximately 2.5 V. The EN_BUCK pin has an internal pullup current source that can be used to adjust the input voltage undervoltage lockout (UVLO) threshold with two external resistors. In addition, the pullup current provides a default condition. When the EN_BUCK pin is floating the device will operate. The operating current is 116 µA when not switching and under no load. When the device is disabled, the supply current is 1.3 µA.

The integrated 200-mΩ high-side MOSFET allows for high–efficiency power supply designs capable of delivering 1.5 A of continuous current to a load. The bias voltage for the integrated high side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high side MOSFET off when the boot voltage falls below a preset threshold. The buck can operate at high duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8-V reference.

The BUCK has a power good comparator (PWRGD) which asserts when the regulated output voltage is less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open-drain output which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the pin to transition high when a pullup resistor is used.

The BUCK minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power good comparator. When the OV comparator is activated, the high-side MOSFET is turned off and masked from turning on until the output voltage is lower than 107%.

The SS_TR (slow start and tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor divider can be coupled to the pin for critical power supply sequencing requirements. The SS_TR pin is discharged before the output powers up. This discharging ensures a repeatable restart after an overtemperature fault,

The BUCK, also, discharges the slow-start capacitor during overload conditions with an overload recovery circuit. The overload recovery circuit will slow-start the output from the fault voltage to the nominal regulation voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent fault conditions to help control the inductor current.

7.3.4 Protection Features

7.3.4.1 Overcurrent Protection and Reporting (OCP)

To protect the power stage from damage due to excessive currents, VDS sensing circuitry is implemented in the DRV8301-Q1. Based on the RDS(on) of the external MOSFETs and the maximum allowed IDS, a voltage threshold can be determined to trigger the overcurrent protection features when exceeded. The voltage threshold is programmed through the SPI registers. Overcurrent protection should be used as a protection scheme only; it is not intended as a precise current regulation scheme. There can be up to a 20% tolerance across channels for the VDS trip point.

Equation 2. VDS = IDS × RDS(on)

The VDS sense circuit measures the voltage from the drain to the source of the external MOSFET while the MOSFET is enabled. The high-side sense is between the PVDD1 and SH_X pins. The low-side sense is between the SH_X and SL_X pins. Ensuring a differential, low impedance connection to the external MOSFETs for these lines will help provide accurate VDS sensing.

Four different overcurrent modes (OC_MODE) can be set through the SPI registers. The OC status bits operate in latched mode. When an overcurrent condition occurs the corresponding OC status bit will latch in the DRV8301-Q1 registers until the fault is reset. After the reset the OC status bit will clear from the register until another overcurrent condition occurs.

  1. Current Limit Mode

    2. In current limit mode the device uses current limiting instead of device shutdown during an overcurrent event. In this mode the device reports overcurrent events through the nOCTW pin. The nOCTW pin will be held low for a maximum 64-µs period (internal timer) or until the next PWM cycle. If another overcurrent event is triggered from another MOSFET, during a previous overcurrent event, the reporting will continue for another 64-µs period (internal timer will restart) or until both PWM signals cycle. The associated status bit will be asserted for the MOSFET in which the overcurrent was detected.

    There are two current control settings in current limit mode. These are set by one bit in the SPI registers. The default mode is cycle by cycle (CBC).

    • Cycle-By-Cycle Mode (CBC): In CBC mode, the MOSFET on which overcurrent has been detected on will shut off until the next PWM cycle.
    • Off-Time Control Mode: In Off-Time mode, the MOSFET in which overcurrent has been detected is disabled for a 64-µs period (set by internal timer). If overcurrent is detected in another MOSFET, the timer will be reset for another 64-µs period and both MOSFETs will be disabled for the duration. During this period, normal operation can be restored for a specific MOSFET with a corresponding PWM cycle.

  2. OC Latch Shutdown Mode

    3. When an overcurrent event occurs, both the high-side and low-side MOSFETs will be disabled in the corresponding half-bridge. The nFAULT pin and nFAULT status bits will be asserted along with the associated status bit for the MOSFET in which the overcurrent was detected. The nFAULT pin, nFAULT status bit, and OC status bit will latch until a reset is received through the GATE_RESET bit or a quick EN_GATE reset pulse.

  3. Report Only Mode

    4. No protective action will be taken in this mode when an overcurrent event occurs. The overcurrent event will be reported through the nOCTW pin (64-µs pulse) and SPI status register. The external MCU should take action based on its own control algorithm.

  4. OC Disabled Mode

    5. The device will ignore and not report all overcurrent detections.

7.3.4.2 Undervoltage Protection (PVDD_UV and GVDD_UV)

To protect the power output stage during start-up, shutdown, and other possible undervoltage conditions, the DRV8301-Q1 provides undervoltage protection by driving the gate drive outputs (GH_X, GL_X) low whenever PVDD or GVDD are below their undervoltage thresholds (PVDD_UV/GVDD_UV). This will put the external MOSFETs in a high impedance state. When the device is in PVDD_UV it will not respond to SPI commands and the SPI registers will revert to their default settings.

A specific PVDD1 undervoltage transient brownout from 13 to 15 µs can cause the DRV8301-Q1 to become unresponsive to external inputs until a full power cycle. The transient condition consists of having PVDD1 greater than the PVDD_UV level and then PVDD1 dropping below the PVDD_UV level for a specific period of 13 to 15 µs. Transients shorter or longer than 13 to 15 µs will not affect the normal operation of the undervoltage protection. Additional bulk capacitance can be added to PVDD1 to reduce undervoltage transients.

7.3.4.3 Overvoltage Protection (GVDD_OV)

The device will shut down both the gate driver and charge pump if the GVDD voltage exceeds the GVDD_OV threshold to prevent potential issues related to the GVDD pin or the charge pump (for example, short of external GVDD cap or charge pump). The fault is a latched fault and can only be reset through a reset transition on the EN_GATE pin.

7.3.4.4 Overtemperature Protection

A two-level overtemperature detection circuit is implemented:

  • Level 1: Over Temperature Warning (OTW)
    OTW is reported through the nOCTW pin (overcurrent and/or overtemperature warning) for default settings. OCTW pin can be set to report OTW or OCW only through the SPI registers. See SPI Communication.
  • Level 2: Over Temperature Latched Shutdown of Gate Driver and Charge Pump (OTSD_GATE)
    OTSD_GATE is reported through the nFAULT pin. This is a latched shutdown, so the gate driver will not recover automatically, even if the overtemperature condition is not present anymore. An EN_GATE reset or SPI (RESET_GATE) is required to recover the gate driver to normal operation after the temperature goes below a preset value, tOTSD_CLR.

SPI operation is still available and register settings will be remaining in the device during OTSD operation as long as PVDD1 is within the defined operation range.

7.3.4.5 Fault and Protection Handling

The nFAULT pin indicates when a shutdown event has occurred. These events include overcurrent, overtemperature, overvoltage, or undervoltage. nFAULT is an open-drain signal. nFAULT will go high when the gate driver is ready for PWM inputs during start-up.

The nOCTW pin indicates when a overcurrent event or overtemperature event has occurred. These events are not necessary related to a shutdown.

Table 3 provides a summary of all the protection features and their reporting structure.

Table 3. Fault and Warning Reporting and Handling

EVENT ACTION LATCH REPORTING ON
nFAULT PIN		 REPORTING ON
nOCTW PIN		 REPORTING IN SPI
STATUS REGISTER
PVDD
undervoltage		 External FETs Hi-Z;
Weak pulldown of all gate
driver output		 N Y N Y
DVDD
undervoltage		 External FETs Hi-Z;
Weak pulldown of all gate
driver output; When recovering,
reset all status registers		 N Y N N
GVDD
undervoltage		 External FETs Hi-Z;
Weak pulldown of all gate
driver output		 N Y N Y
GVDD
overvoltage		 External FETs Hi-Z;
Weak pulldown of all gate driver output
Shutdown the charge pump
Won’t recover and reset through
SPI reset command or
quick EN_GATE toggling		 Y Y N Y
OTW None N N Y (in default setting) Y
OTSD_GATE Gate driver latched shutdown.
Weak pulldown of all gate driver output
to force external FETs Hi-Z
Shut down the charge pump		 Y Y Y Y
OTSD_BUCK OTSD of Buck Y N N N
Buck output
undervoltage		 UVLO_BUCK: auto-restart N Y (PWRGD pin) N N
Buck overload Buck current limiting
(Hi-Z high side until current reaches
zero and then auto-recovering)		 N N N N
External FET
overload – current limit mode		 External FETs current limiting
(only OC detected FET)		 N N Y Y
External FET
overload – Latch mode		 Weak pulldown of gate driver
output and PWM logic “0” of
LS and HS in the same phase.
External FETs Hi-Z		 Y Y Y Y
External FET
overload – reporting only mode		 Reporting only N N Y Y

7.3.5 Start-up and Shutdown Sequence Control

During power up all gate drive outputs are held low. Normal operation of gate driver and current shunt amplifiers can be initiated by toggling EN_GATE from a low state to a high state. If no errors are present, the DRV8301-Q1 is ready to accept PWM inputs. Gate driver always has control of the power FETs even in gate disable mode as long as PVDD is within functional region.

There is an internal diode from SDO to VDD_SPI, so VDD_SPI is required to be powered to the same power level as other SPI devices (if there is any SDO signal from other devices) all the time. VDD_SPI supply should be powered up first before any signal appears at SDO pin and powered down after completing all communications at SDO pin.

7.4 Device Functional Modes

7.4.1 EN_GATE

EN_GATE low is used to put gate driver, charge pump, current shunt amplifier, and internal regulator blocks into a low-power consumption mode to save energy. SPI communication is not supported during this state and the SPI registers will revert to their default settings after a full EN_GATE reset. The device will put the MOSFET output stage to high-impedance mode as long as PVDD is still present.

When the EN_GATE pin goes low to high, it will go through a power-up sequence, and enable gate driver, current amplifiers, charge pump, internal regulator, and so forth and reset all latched faults related to gate driver block. The EN_GATE will also reset status registers in the SPI table. All latched faults can be reset when EN_GATE is toggled after an error event unless the fault is still present.

When EN_GATE goes from high to low, it will shut down gate driver block immediately, so gate output can put external FETs in high impedance mode. It will then wait for 10 µs before completely shutting down the rest of the blocks. A quick fault reset mode can be done by toggling EN_GATE pin for a very short period (less than 10 µs). This will prevent the device from shutting down the other functional blocks such as charge pump and internal regulators and bring a quicker and simple fault recovery. SPI will still function with such a quick EN_GATE reset mode. To perform a full reset, EN_GATE should be toggled for longer than 20 µs. This allows for all of the blocks to completely shut down and reach known states.

An EN_GATE reset pulse (high → low → high) from 10 to 20 µs should not be applied to the EN_GATE pin. The DRV8301-Q1 has a transition area from the quick to full reset modes that can cause the device to become unresponsive to external inputs until a full power cycle. An RC filter can be added externally to the pin if reset pulses with this period are expected to occur on the EN_GATE pin.

The other way to reset all of the faults is to use SPI command (RESET_GATE), which will only reset gate driver block and all the SPI status registers without shutting down the other functional blocks.

One exception is to reset a GVDD_OV fault. A quick EN_GATE quick fault reset or SPI command reset will not work with GVDD_OV fault. A complete EN_GATE with low level holding longer than 20 µs is required to reset GVDD_OV fault. TI highly recommends to inspect the system and board when GVDD_OV occurs.

7.4.2 DTC

Dead time can be programmed through DTC pin. A resistor should be connected from DTC to ground to control the dead time. Dead time control range is from 50 ns to 500 ns. Short DTC pin to ground will provide minimum dead time (50 ns). Resistor range is 0 to 150 kΩ. Dead time is linearly set over this resistor range.

Current shoot-through prevention protection will be enabled in the device all time independent of dead time setting and input mode setting.

7.4.3 VDD_SPI

VDD_SPI is the power supply to power SDO pin. It has to be connected to the same power supply (3.3 V or 5 V) that MCU uses for its SPI operation.

During power-up or power-down transient, VDD_SPI pin could be zero voltage shortly. During this period, no SDO signal should be present at SDO pin from any other devices in the system because it causes a parasitic diode in the DRV8301-Q1 conducting from SDO to VDD_SPI pin as a short. This should be considered and prevented from system power sequence design.

7.5 Programming

7.5.1 SPI Communication

7.5.1.1 SPI

The DRV8301-Q1 SPI operates as a slave. The SPI input (SDI) data format consists of a 16 bit word with 1 read/write bit, 4 address bits, and 11 data bits. The SPI output (SDO) data format consists of a 16 bit word with 1 frame fault bit, 4 address bits, and 11 data bits. When a frame is not valid, frame fault bit will set to 1 and the remaining bits will shift out as 0.

A valid frame must meet following conditions:

  • Clock must be low when nSCS goes low.
  • Should have 16 full clock cycles.
  • Clock must be low when nSCS goes high.

When nSCS is asserted high, any signals at the SCLK and SDI pins are ignored and SDO is forced into a high impedance state. When nSCS transitions from HIGH to LOW, SDO is enabled and the SDO response word loads into the shift register based on the previous SPI input word.

The SCLK pin must be low when nSCS transitions low. While nSCS is low, at each rising edge of the clock the response word is serially shifted out on the SDO pin with the MSB shifted out first.

While SCS is low, at each falling edge of the clock the new input word is sampled on the SDI pin. The SPI input word is decoded to determine the register address and access type (read or write). The MSB will be shifted in first. Any amount of time may pass between bits, as long as nSCS stays active low. This allows two 8-bit words to be used. If the input word sent to SDI is less than 16 bits or more than 16 bits, it is considered a frame error. If it is a write command, the data will be ignored. The fault bit in the next SDO response word will then report 1. After the 16th clock cycle or when nSCS transitions from LOW to HIGH, the SDI shift register data is transferred into a latch where the input word is decoded.

For a READ command (Nth cycle) sent to SDI, SDO will respond with the data at the specified address in the next cycle. (N+1)

For a WRITE command (Nth cycle) sent to SDI, SDO will respond with the data in Status Register 1 (0x00) in the next cycle (N+1). This feature is intended to maximize SPI communication efficiency when having multiple write commands.

7.5.1.2 SPI Format

The SDI input data word is 16 bits long and consists of:

  • 1 read/write bit W [15]
  • 4 address bits A [14:11]
  • 11 data bits D [10:0]

The SDO output data word is 16 bits long and consists of:

  • 1 fault frame bit F [15]
  • 4 address bits A [14:11]
  • 11 data bits D [10:0]

The SDO output word (Nth cycle) is in response to the previous SDI input word (N-1 cycle).

Therefore each SPI Query/Response pair requires two full 16 bit shift cycles to complete.

Table 4. SPI Input Data Control Word Format

R/W ADDRESS DATA
Word Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Command W0 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 5. SPI Output Data Response Word Format

R/W DATA
Word Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Command F0 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

7.6 Register Maps

7.6.1 Read / Write Bit

The MSB bit of the SDI input word (W0) is a read/write bit. When W0 = 0, the input word is a write command. When W0 = 1, input word is a read command.

7.6.2 Address Bits

Table 6. Register Address

REGISTER TYPE ADDRESS [A3..A0] REGISTER NAME DESCRIPTION READ AND WRITE ACCESS
Status Register 0 0 0 0 Status Register 1 Status register for device faults R
0 0 0 1 Status Register 2 Status register for device faults and ID R
Control Register 0 0 1 0 Control Register 1 R/W
0 0 1 1 Control Register 2 R/W

7.6.3 SPI Data Bits

7.6.3.1 Status Registers

Table 7. Status Register 1 (Address: 0x00) (All Default Values are Zero)

ADDRESS REGISTER NAME D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0x00 Status Register 1 FAULT GVDD_UV PVDD_UV OTSD OTW FETHA_OC FETLA_OC FETHB_OC FETLB_OC FETHC_OC FETLC_OC

Table 8. Status Register 2 (Address: 0x01) (All Default Values are Zero)

ADDRESS REGISTER NAME D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0x01 Status Register 2 GVDD_OV Device ID [3] Device ID [2] Device ID [1] Device ID [0]

7.6.3.2 Control Registers

Table 9. Control Register 1 for Gate Driver Control (Address: 0x02)(1)

ADDRESS NAME DESCRIPTION D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0x02 GATE_CURRENT Gate drive peak current 1.7 A 0(1) 0(1)
Gate drive peak current 0.7 A 0 1
Gate drive peak current 0.25 A 1 0
Reserved 1 1
GATE_RESET Normal mode 0(1)
Reset gate driver latched faults (reverts to 0) 1
PWM_MODE 6 PWM inputs (see Table 1) 0(1)
3 PWM inputs (see Table 2) 1
OCP_MODE Current limit 0(1) 0(1)
OC latch shut down 0 1
Report only 1 0
OC disabled 1 1
OC_ADJ_SET See OC_ADJ_SET table X X X X X
(1) Default value

Table 10. Control Register 2 for Current Shunt Amplifiers and Misc Control (Address: 0x03)(1)

ADDRESS NAME DESCRIPTION D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0x03 OCTW_MODE Report both OT and OC at nOCTW pin 0(1) 0(1)
Report OT only 0 1
Report OC only 1 0
Report OC only (reserved) 1 1
GAIN Gain of shunt amplifier: 10 V/V 0(1) 0(1)
Gain of shunt amplifier: 20 V/V 0 1
Gain of shunt amplifier: 40 V/V 1 0
Gain of shunt amplifier: 80 V/V 1 1
DC_CAL_CH1 Shunt amplifier 1 connects to load through input pins 0(1)
Shunt amplifier 1 shorts input pins and disconnects from load for external calibration 1
DC_CAL_CH2 Shunt amplifier 2 connects to load through input pins 0(1)
Shunt amplifier 2 shorts input pins and disconnects from load for external calibration 1
OC_TOFF Cycle by cycle 0(1)
Off-time control 1
Reserved
(1) Default value

7.6.3.3 Overcurrent Adjustment

Table 11. OC_ADJ_SET Table

Control Bit (D6–D10) (0xH) 0 1 2 3 4 5 6 7
Vds (V) 0.06 0.068 0.076 0.086 0.097 0.109 0.123 0.138
Control Bit (D6–D10) (0xH) 8 9 10 11 12 13 14 15
Vds (V) 0.155 0.175 0.197 0.222 0.250 0.282 0.317 0.358
Control Bit (D6–D10) (0xH) 16 17 18 19 20 21 22 23
Vds (V) 0.403 0.454 0.511 0.576 0.648 0.730 0.822 0.926
Code Number (0xH) 24 25 26 27 28 29 30 31
Vds (V) 1.043 1.175 1.324 1.491 1.679(1) 1.892(1) 2.131(1) 2.400(1)
(1) Do not use settings 28, 29, 30, 31 for VDS sensing if the IC is expected to operate in the 6-V to 8-V range.