SLOS842A September   2013  – June 2015 DRV8301-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Buck Converter Characteristics
    7. 6.7  Current Shunt Amplifier Characteristics
    8. 6.8  Gate Timing and Protection Characteristics
    9. 6.9  SPI Timing Requirements (Slave Mode Only)
    10. 6.10 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Function Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three-Phase Gate Driver
      2. 7.3.2 Current Shunt Amplifiers
      3. 7.3.3 Buck Converter
      4. 7.3.4 Protection Features
        1. Overcurrent Protection and Reporting (OCP)
        2. Undervoltage Protection (PVDD_UV and GVDD_UV)
        3. Overvoltage Protection (GVDD_OV)
        4. Overtemperature Protection
        5. Fault and Protection Handling
      5. 7.3.5 Start-up and Shutdown Sequence Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 EN_GATE
      2. 7.4.2 DTC
      3. 7.4.3 VDD_SPI
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. SPI
        2. SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 Read / Write Bit
      2. 7.6.2 Address Bits
      3. 7.6.3 SPI Data Bits
        1. Status Registers
        2. Control Registers
        3. Overcurrent Adjustment
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Gate Driver Start-up Issue Errata
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Gate Drive Average Current Load
        2. Overcurrent Protection Setup
        3. Sense Amplifier Setup
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV8301-Q1 is a gate driver designed to drive a 3-phase BLDC motor in combination with external power MOSFETs. The device provides a high level of integration with three half-bridge gate drivers, two current shunt amplifiers, overcurrent protection, and a step-down buck regulator.

8.1.1 Gate Driver Start-up Issue Errata

The DRV8301-Q1 gate drivers may not correctly power up if a voltage greater than 8.5 V is present on any SH_X pin when EN_GATE is first brought logic high (device first enabled) after PVDD1 power is applied. This situation should be avoided by ensuring the voltage levels on the SH_X pins are less than 8.5 V when the DRV8301-Q1 is first enabled. After the first successful enable, EN_GATE can be brought low or high regardless of the SH_X pin voltage with no impact to the device operation.

8.2 Typical Application

The following design is a common application of the DRV8301-Q1.

DRV8301-Q1 schem_slos842.gifFigure 7. Typical Application Schematic

8.2.1 Design Requirements

Table 12. Design Parameters

Supply voltage PVDD 24 V
Motor winding resistance MR 0.5 Ω
Motor winding inductance ML 0.28 mH
Motor poles MP 16 poles
Motor rated RPM MRPM 4000 RPM
Target full-scale current IMAX 14 A
Sense resistor RSENSE 0.01 Ω
MOSFET Qg Qg 29 nC
MOSFET RDS(on) RDS(on) 4.7 mΩ
VDS trip level OC_ADJ_SET 0.123 V
Switching frequency ƒSW 45 kHz
Series gate resistance RGATE 10 Ω
Amplifier reference VREF 3.3 V
Amplifier gain Gain 10 V/V

8.2.2 Detailed Design Procedure

Table 13. Gate Driver External Components

RnOCTW nOCTW VCC(1) ≥10 kΩ
RDTC DTC GND (PowerPAD) 0 to 150 kΩ (50 ns to 500 ns)
CGVDD GVDD GND (PowerPAD) 2.2 µF (20%) ceramic, ≥ 16 V
CCP CP1 CP2 0.022 µF (20%) ceramic, rated for PVDD1
CDVDD DVDD AGND 1 µF (20%) ceramic, ≥ 6.3 V
CAVDD AVDD AGND 1 µF (20%) ceramic, ≥ 10 V
CPVDD1 PVDD1 GND (PowerPAD) ≥4.7 µF (20%) ceramic, rated for PVDD1
CBST_X BST_X SH_X 0.1 µF (20%) ceramic, ≥ 16 V
(1) VCC is the logic supply to the MCU

Table 14. Buck Regulator External Components

RRT_CLK RT_CLK GND (PowerPAD) See Buck Converter
CCOMP COMP GND (PowerPAD) See Buck Converter
RCCOMP COMP GND (PowerPAD) See Buck Converter
RVSENSE1 PH (Filtered) VSENSE See Buck Converter
RVSENSE2 VSENSE GND (PowerPAD) See Buck Converter
LPH PH PH (Filtered) See Buck Converter
DPH PH GND (PowerPAD) See Buck Converter
CPH PH (Filtered) GND (PowerPAD) See Buck Converter
CBST_BK BST_BK PH See Buck Converter
CPVDD2 PVDD2 GND (PowerPAD) ≥4.7 µF (20%) ceramic, rated for PVDD2
CSS_TR SS_TR GND (PowerPAD) See Buck Converter
(1) VCC is the logic supply to the MCU Gate Drive Average Current Load

The gate drive supply (GVDD) of the DRV8301-Q1 can deliver up to 30 mA (RMS) of current to the external power MOSFETs. Use Equation 3 to determine the approximate RMS load on the gate drive supply:

Equation 3. Gate Drive RMS Current = MOSFET Qg × Number of Switching MOSFETs × Switching Frequency


7.83 mA = 29 nC × 6 × 45 kHz

This is a rough approximation only. Overcurrent Protection Setup

The DRV8301-Q1 provides overcurrent protection for the external power MOSFETs through the use of VDS monitors for both the high side and low side MOSFETs. These are intended for protecting the MOSFET in overcurrent conditions and not for precise current regulation.

The overcurrent protection works by monitoring the VDS voltage of the external MOSFET and comparing it against the OC_ADJ_SET register value. If the VDS exceeds the OC_ADJ_SET value the DRV8301-Q1 takes action according to the OC_MODE register.

Equation 4. Overcurrent Trip = OC_ADJ_SET / MOSFET RDS(on)


26.17 A = 0.123 V/ 4.7 mΩ

MOSFET RDS(on) changes with temperature and this will affect the overcurrent trip level. Sense Amplifier Setup

The DRV8301-Q1 provides two bidirectional low-side current shunt amplifiers. These can be used to sense a sum of the three half-bridges, two of the half-bridges individually, or in conjunction with an additional shunt amplifier to sense all three half-bridges individually.

  1. Determine the peak current that the motor will demand (IMAX). This will be dependent on the motor parameters and your specific application. I(MAX) in this example is 14 A.
  2. Determine the available voltage range for the current shunt amplifier. This will be ± half of the amplifier reference voltage (VREF). In this case the available range is ±1.65 V.
  3. Determine the sense resistor value and amplifier gain settings. There are common tradeoffs for both the sense resistor value and amplifier gain. The larger the sense resistor value, the better the resolution of the half-bridge current. This comes at the cost of additional power dissipated from the sense resistor. A larger gain value will allow you to decrease the sense resistor, but at the cost of increased noise in the output signal. This example uses a 0.01-Ω sense resistor and the minimum gain setting of the DRV8301-Q1 (10 V/V). These values allow the current shunt amplifiers to measure ±16.5 A (some additional margin on the 14 A requirement).

8.2.3 Application Curves

DRV8301-Q1 wvfrm01_los719.png
Figure 8. Motor Spinning 2000 RPM
DRV8301-Q1 wvfrm03_los719.png
Figure 10. Gate Drive 20% Duty Cycle
DRV8301-Q1 wvfrm02_los719.png
Figure 9. Motor Spinning 4000 RPM
DRV8301-Q1 wvfrm04_los719.png
Figure 11. Gate Drive 80% Duty Cycle