SLVSFN2B September   2021  – February 2022 DRV8311

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 SPI Secondary Device Mode Timings
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Stage
      2. 8.3.2  Control Modes
        1. 8.3.2.1 6x PWM Mode (DRV8311S and DRV8311H variants only)
        2. 8.3.2.2 3x PWM Mode (DRV8311S and DRV8311H variants only)
        3. 8.3.2.3 PWM Generation Mode (DRV8311S and DRV8311P Variants)
      3. 8.3.3  Device Interface Modes
        1. 8.3.3.1 Serial Peripheral Interface (SPI)
        2. 8.3.3.2 Hardware Interface
      4. 8.3.4  AVDD Linear Voltage Regulator
      5. 8.3.5  Charge Pump
      6. 8.3.6  Slew Rate Control
      7. 8.3.7  Cross Conduction (Dead Time)
      8. 8.3.8  Propagation Delay
      9. 8.3.9  Pin Diagrams
        1. 8.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 8.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 8.3.9.3 Open Drain Pin
        4. 8.3.9.4 Push Pull Pin
        5. 8.3.9.5 Four Level Input Pin
      10. 8.3.10 Current Sense Amplifiers
        1. 8.3.10.1 Current Sense Amplifier Operation
        2. 8.3.10.2 Current Sense Amplifier Offset Correction
      11. 8.3.11 Protections
        1. 8.3.11.1 VM Supply Undervoltage Lockout (NPOR)
        2. 8.3.11.2 Under Voltage Protections (UVP)
        3. 8.3.11.3 Overcurrent Protection (OCP)
          1. 8.3.11.3.1 OCP Latched Shutdown (OCP_MODE = 010b)
          2. 8.3.11.3.2 OCP Automatic Retry (OCP_MODE = 000b or 001b)
          3. 8.3.11.3.3 OCP Report Only (OCP_MODE = 011b)
          4. 8.3.11.3.4 OCP Disabled (OCP_MODE = 111b)
        4. 8.3.11.4 Thermal Protections
          1. 8.3.11.4.1 Thermal Warning (OTW)
          2. 8.3.11.4.2 Thermal Shutdown (OTSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
    5. 8.5 SPI Communication
      1. 8.5.1 Programming
        1. 8.5.1.1 SPI and tSPI Format
  9. 9 DRV8311 Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Three-Phase Brushless-DC Motor Control
        1. 10.2.1.1 Detailed Design Procedure
          1. 10.2.1.1.1 Motor Voltage
        2. 10.2.1.2 Driver Propagation Delay and Dead Time
        3. 10.2.1.3 Delay Compensation
        4. 10.2.1.4 Current Sensing and Output Filtering
        5. 10.2.1.5 Application Curves
    3. 10.3 Three Phase Brushless-DC tSPI Motor Control
      1. 10.3.1 Detailed Design Procedure
    4. 10.4 Alternate Applications
  11. 11Power Supply Recommendations
    1. 11.1 Bulk Capacitance
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
      1. 12.3.1 Power Dissipation and Junction Temperature Estimation
  13. 13Device and Documentation Support
    1. 13.1 Support Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2.3 PWM Generation Mode (DRV8311S and DRV8311P Variants)

In PWM generation mode, the PWM signals are generated internally in the DRV8311 and can be controlled via a SPI (DRV8311S) or tSPI (DRV8311P) register read/write. This operation mode removes the need for controlling the motor through the INHx and INLx pins. The PWM period, frequency, and duty cycle for each phase can be configured over the serial interface. A PWM_SYNC pin functionality allows synchronization between the MCU and DRV8311. The PWM modes can be configured to enable or disable the high-side or low-side MOSFET PWM control for each phase in order to allow for continuous or discontinuous switching whenever required. When using the DRV8311S in PWM Generation mode, connect the PWM_SYNC signal from MCU to the INLB pin of DRV8311S. The DRV8311S does not care about the state of all other INHx and INLx pins in this mode. Trapezoidal, sinusoidal, and FOC control are all possible using PWM generation mode.

Figure 8-6 PWM Generation Mode - DRV8311P
Figure 8-7 PWM Generation Mode - DRV8311S

PWM generation mode has three different options: up/down mode, up mode, and down mode. The PWM generation mode can be configured using PWMCNTR_MODE bits in the PWMG_CTRL register. The duty cycle defined by the PWM_DUTY_OUTx bits in the PWMG_x_DUTY register (x for each phase A, B, C) of each phase is compared against the reference counter signal to generate the high side MOSFET PWM. The PWM generation uses a reference counter signal generated internally based on the configuration of PWM_PRD_OUT bits (PWMG_PERIOD register) and PWMCNTR_MODE bits. If PWM_EN bit is high, the high side MOSFET PWM output is high when PWM_DUTY_OUTx is greater than the reference counter. For PWM_EN being low, the output is always held low. To achieve 100% duty cycle for the high side MOSFET [HS_ON for entire cycle], the PWM_DUTY_OUTx value must be higher than the PWM_PRD_OUT value.

In up/down mode [PWMCNTR_MODE = 0h], the reference counter waveform resembles a V shape, counting down from the PWM_PRD_OUT value when enabled and then counting up again once counter reaches zero. Configure the PWM_PRD_OUT bits to generate a PWM frequency (FPWM) using the relation PWM_PRD_OUT = 0.5 x (FSYS /FPWM). FSYS is the internal system clock frequency (approximately 20MHz) of DRV8311P and DRV8311S.

Figure 8-8 PWM Generation - Up/Down Mode

In up mode [PWMCNTR_MODE = 1h], the counter counts up from zero until it reaches the PWM_PRD_OUT value and then resets to zero. PWM_PRD_OUT = FSYS /FPWM

Figure 8-9 PWM Generation - Up Mode

In down mode [PWMCNTR_MODE = 2h], the counter counts down from the PWM_PRD_OUT value until it reaches zero and then resets to PWM_PRD_OUT value. PWM_PRD_OUT = FSYS /FPWM

Figure 8-10 PWM Generation - Down Mode

The dead time configured by the TDEAD_CTRL register is inserted between the LS_ON falling edge and the HS_ON rising edge as well as between HS_ON falling edge and LS_ON rising edge.

PWM Synchronization in PWM Generation Mode

When there is no dedicated INHx or INLx control signals, the external MCU can lose synchronization with PWM signal generated by the DRV8311. For synchronization, the external MCU sends one reference signal to the PWM_SYNC pin. PWM synchronization helps to generate the DRV8311 PWM output with the accuracy of the MCU clock and aligns PWM outputs with the MCU's ADC sampling the current sense outputs. The PWM_SYNC signal can also help to measure the DRV8311 internal oscillator frequency. DRV8311 also support auto-calibration of internal oscillator to calibrate the oscillator at 20MHz regardless of operating conditions. The DRV8311 allows five different methods of synchronizing between MCU and DRV8311 by configuring the PWM_OSC_SYNC bits of PWMG_CTRL register. The different synchronization methods are outlined below.

PWM_OSC_SYNC = 1h: The DRV8311 measures the PWM_SYNC signal period (PWM_SYNC_PRD) in counts of DRV8311 system clock FSYS (approximately 20MHz). The MCU reads the register PWM_SYNC_PRD and can calibrate the PWM period. For example, assume that the MCU generate a 50% duty PWM_SYNC signal using an MCU timer with a period count of N and clock frequency FMCU. The MCU read the PWM_SYNC_PERIOD register value say M, generated by DRV8311. The DRV8311 generates the PWM_SYNC_PERIOD using the DRV8311 system clock FSYS(DRV). Now the MCU timer clock and the DRV8311 system clock are related by the equation FMCU x M = FSYS(DRV) x N.

The PWM_SYNC_PRD is 12bit and with DRV8311 internal system clock of approximately 20MHz, the minimum PWM_SYNC frequency that can be read without saturation is approximately 4.885 kHz (FSYS/4095).

PWM_OSC_SYNC = 2h: The PWM_SYNC signal from the MCU is used to set the PWM period of DRV8311 and PWMG_PERIOD register setting is ignored. DRV8311 resets the PWM counter on rising edge of the PWM_SYNC.

Figure 8-11 PWM Synchronization in Up/down Mode (PWM_OSC_SYNC = 2h)
Figure 8-12 PWM Synchronization in Up Mode (PWM_OSC_SYNC = 2h)
Figure 8-13 PWM Synchronization in Down Mode (PWM_OSC_SYNC = 2h)

PWM_OSC_SYNC = 5h: PWM_SYNC is used for DRV8311 internal oscillator synchronization (only 20 kHz frequency supported). For a PWM_SYNC signal of 20kHz, DRV8311 counts the number of internal system oscillator clock pulses between the rising edges of PWM_SYNC signal. For DRV8311 system clock at 20MHz, the number of clock pulses are expected to be 1000 in the ideal case. Deviation from this number implies an error in either the oscillator frequency generated by DRV8311 or the PWM_SYNC frequency from the MCU. The PWM_SYNC frequency from MCU is assumed accurate and DRV8311 does oscillator calibration internally to calibrate the frequency at 20MHz and hence align PWM frequency generated with PWM_SYNC.

PWM_OSC_SYNC = 6h: PWM_SYNC is used for DRV8311 internal system oscillator calibration and setting PWM period (only 20 kHz frequency supported). The PWMG_PERIOD register setting is ignored. DRV8311 resets the PWM reference counter on rising edge of the PWM_SYNC.

PWM_OSC_SYNC = 7h: The SPI Clock pin SCLK is used for the DRV8311 internal system oscillator calibration to 20MHz. In this mode, the user has to configure the SPI clock frequency for synchronizing the oscillator (SPICLK_FREQ_SYNC) and the number of SPI clock cycles required for synchronizing the oscillator (SPISYNC_ACRCY) by configuring the PWMG_CTRL Register. The DRV8311 measures the total time for the entire SPI clock cycles (configured by SPISYNC_ACRCY) in counts of DRV8311 internal system clock FSYS and calibrates the internal system clock to match the counts expected for 20MHz frequency. The DRV8311 system oscillator frequency accuracy after calibration compared to 20MHz depends on the configuration of SPISYNC_ACRCY.