SLVSH52 Data sheet

SLVSH52 February 2023 DRV8316C-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RGF|40
- MPQF173F

Thermal pad, mechanical data (Package|Pins)

RGF|40
- QFND710

Orderable Information

8.6.2 CONTROL Registers

#GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_TABLE_1_TABLE lists the memory-mapped registers for the CONTROL registers. All register offset addresses not listed in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_TABLE_1_TABLE should be considered as reserved locations and the register contents should not be modified.

Table 8-16 CONTROL Registers

Offset	Acronym	Register Name	Section
3h	Control Register 1	Control Register 1	Control Register 1 (Offset = 3h) [Reset = 00h]
4h	Control Register 2	Control Register 2	Control Register 2 (Offset = 4h) [Reset = 60h]
5h	Control Register 3	Control Register 3	Control Register 3 (Offset = 5h) [Reset = 46h]
6h	Control Register 4	Control Register 4	Control Register 4 (Offset = 6h) [Reset = 10h]
7h	Control Register 5	Control Register 5	Control Register 5 (Offset = 7h) [Reset = 00h]
8h	Control Register 6	Control Register 6	Control Register 6 (Offset = 8h) [Reset = 00h]
Ch	Control Register 10	Control Register 10	Control Register 10 (Offset = Ch) [Reset = 00h]

Complex bit access types are encoded to fit into small table cells. #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_LEGEND_TABLE shows the codes that are used for access types in this section.

Table 8-17 CONTROL Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
R-0	R -0	Read Returns 0s
Write Type
W	W	Write
W1C	W 1C	Write 1 to clear
WAPU	W APU	Write Atomic write with password unlock
Reset or Default Value
-n		Value after reset or the default value

8.6.2.1 Control Register 1 (Offset = 3h) [Reset = 00h]

Control Register 1 is shown in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_CONTROL_CTRL1_FIGURE_TABLE and described in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_CONTROL_CTRL1_TABLE_TABLE.

Return to the Summary Table.

Figure 8-51 Control Register 1

7	6	5	4	3	2	1	0
RESERVED					REG_LOCK
R-0-0h					R/WAPU-0h

Table 8-18 Control Register 1 Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R-0	0h	Reserved
2-0	REG_LOCK	R/WAPU	0h	Register Lock Bits 0h = No effect unless locked or unlocked 1h = No effect unless locked or unlocked 2h = No effect unless locked or unlocked 3h = Write 011b to this register to unlock all registers 4h = No effect unless locked or unlocked 5h = No effect unless locked or unlocked 6h = Write 110b to lock the settings by ignoring further register writes except to these bits and address 0x03h bits 2-0. 7h = No effect unless locked or unlocked

8.6.2.2 Control Register 2 (Offset = 4h) [Reset = 60h]

Control Register 2 is shown in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_CONTROL_CTRL2_FIGURE_TABLE and described in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_CONTROL_CTRL2_TABLE_TABLE.

Return to the Summary Table.

Figure 8-52 Control Register 2

7	6	5	4	3	2	1	0
RESERVED		SDO_MODE	SLEW		PWM_MODE		CLR_FLT
R/W-1h		R/W-1h	R/W-0h		R/W-0h		W1C-0h

Table 8-19 Control Register 2 Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	1h	Reserved
5	SDO_MODE	R/W	1h	SDO Mode Setting 0h = SDO IO in Open Drain Mode 1h = SDO IO in Push Pull Mode
4-3	SLEW	R/W	0h	Slew Rate Settings 0h = Slew rate is 25 V/µs 1h = Slew rate is 50 V/µs 2h = Slew rate is 125 V/µs 3h = Slew rate is 200 V/µs
2-1	PWM_MODE	R/W	0h	Device Mode Selection 0h = 6x mode 1h = 6x mode with current limit 2h = 3x mode 3h = 3x mode with current limit
0	CLR_FLT	W1C	0h	Clear Fault 0h = No clear fault command is issued 1h = To clear the latched fault bits. This bit automatically resets after being written.

8.6.2.3 Control Register 3 (Offset = 5h) [Reset = 46h]

Control Register 3 is shown in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_CONTROL_CTRL3_FIGURE_TABLE and described in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_CONTROL_CTRL3_TABLE_TABLE.

Return to the Summary Table.

Figure 8-53 Control Register 3

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED	PWM_100_DUTY_SEL	OVP_SEL	OVP_EN	SPI_FLT_REP	OTW_REP
R-0-0h	R/W-1h	R/W-0h	R/W-0h	R/W-0h	R/W-1h	R/W-1h	R/W-0h

Table 8-20 Control Register 3 Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R-0	0h	Reserved
6	RESERVED	R/W	1h	Reserved
5	RESERVED	R/W	0h	Reserved
4	PWM_100_DUTY_SEL	R/W	0h	Freqency of PWM at 100% Duty Cycle 0h = 20KHz 1h = 40KHz
3	OVP_SEL	R/W	0h	Overvoltage Level Setting 0h = VM overvoltage level is 34-V 1h = VM overvoltage level is 22-V
2	OVP_EN	R/W	1h	Overvoltage Enable Bit 0h = Overvoltage protection is disabled 1h = Overvoltage protection is enabled
1	SPI_FLT_REP	R/W	1h	SPI Fault Reporting Disable Bit 0h = SPI fault reporting on nFAULT pin is enabled 1h = SPI fault reporting on nFAULT pin is disabled
0	OTW_REP	R/W	0h	Overtemperature Warning Reporting Bit 0h = Over temperature reporting on nFAULT is disabled 1h = Over temperature reporting on nFAULT is enabled

8.6.2.4 Control Register 4 (Offset = 6h) [Reset = 10h]

Control Register 4 is shown in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_CONTROL_CTRL4_FIGURE_TABLE and described in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_CONTROL_CTRL4_TABLE_TABLE.

Return to the Summary Table.

Figure 8-54 Control Register 4

7	6	5	4	3	2	1	0
DRV_OFF	OCP_CBC	OCP_DEG		OCP_RETRY	OCP_LVL	OCP_MODE
R/W-0h	R/W-0h	R/W-1h		R/W-0h	R/W-0h	R/W-0h

Table 8-21 Control Register 4 Field Descriptions

Bit	Field	Type	Reset	Description
7	DRV_OFF	R/W	0h	Driver OFF Bit 0h = No Action 1h = Hi-Z FETs
6	OCP_CBC	R/W	0h	OCP PWM Cycle Operation Bit 0h = OCP clearing in PWM input cycle change is disabled 1h = OCP clearing in PWM input cycle change is enabled
5-4	OCP_DEG	R/W	1h	OCP Deglitch Time Settings 0h = OCP deglitch time is 0.2 µs 1h = OCP deglitch time is 0.6 µs 2h = OCP deglitch time is 1.25 µs 3h = OCP deglitch time is 1.6 µs
3	OCP_RETRY	R/W	0h	OCP Retry Time Settings 0h = OCP retry time is 5 ms 1h = OCP retry time is 500 ms
2	OCP_LVL	R/W	0h	Overcurrent Level Setting 0h = OCP level is 16 A 1h = OCP level is 24 A
1-0	OCP_MODE	R/W	0h	OCP Fault Options 0h = Overcurrent causes a latched fault 1h = Overcurrent causes an automatic retrying fault 2h = Overcurrent is report only but no action is taken 3h = Overcurrent is not reported and no action is taken

8.6.2.5 Control Register 5 (Offset = 7h) [Reset = 00h]

Control Register 5 is shown in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_CONTROL_CTRL5_FIGURE_TABLE and described in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_CONTROL_CTRL5_TABLE_TABLE.

Return to the Summary Table.

Figure 8-55 Control Register 5

7	6	5	4	3	2	1	0
RESERVED	ILIM_RECIR	RESERVED	RESERVED	EN_AAR	EN_ASR	CSA_GAIN
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 8-22 Control Register 5 Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0h	Reserved
6	ILIM_RECIR	R/W	0h	Current Limit Recirculation Settings 0h = Current recirculation through FETs (Brake Mode) 1h = Current recirculation through diodes (Coast Mode)
5	RESERVED	R/W	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3	EN_AAR	R/W	0h	Active Asynshronous Rectification Enable Bit 0h = AAR mode is disabled 1h = AAR mode is enabled
2	EN_ASR	R/W	0h	Active Synchronous Rectification Enable Bit 0h = ASR mode is disabled 1h = ASR mode is enabled
1-0	CSA_GAIN	R/W	0h	Current Sense Amplifier's Gain Settings 0h = CSA gain is 0.15 V/A 1h = CSA gain is 0.3 V/A 2h = CSA gain is 0.6 V/A 3h = CSA gain is 1.2 V/A

8.6.2.6 Control Register 6 (Offset = 8h) [Reset = 00h]

Control Register 6 is shown in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_CONTROL_CTRL6_FIGURE_TABLE and described in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_CONTROL_CTRL6_TABLE_TABLE.

Return to the Summary Table.

Figure 8-56 Control Register 6

7	6	5	4	3	2	1	0
RESERVED		RESERVED	BUCK_PS_DIS	BUCK_CL	BUCK_SEL		BUCK_DIS
R-0-0h		R/W-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

Table 8-23 Control Register 6 Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R-0	0h	Reserved
5	RESERVED	R/W	0h	Reserved
4	BUCK_PS_DIS	R/W	0h	Buck Power Sequencing Disable Bit 0h = Buck power sequencing is enabled 1h = Buck power sequencing is disabled
3	BUCK_CL	R/W	0h	Buck Current Limit Setting 0h = Buck regulator current limit is set to 600 mA 1h = Buck regulator current limit is set to 150 mA
2-1	BUCK_SEL	R/W	0h	Buck Voltage Selection 0h = Buck voltage is 3.3 V 1h = Buck voltage is 5.0 V 2h = Buck voltage is 4.0 V 3h = Buck voltage is 5.7 V
0	BUCK_DIS	R/W	0h	Buck Disable Bit 0h = Buck regulator is enabled 1h = Buck regulator is disabled

8.6.2.7 Control Register 10 (Offset = Ch) [Reset = 00h]

Control Register 10 is shown in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_CONTROL_CTRL10_FIGURE_TABLE and described in #GUID-20221209-SS0T-KDMS-73NG-SZMV2Q1TC4VC/CONTROL_CONTROL_CONTROL_CTRL10_TABLE_TABLE.

Return to the Summary Table.

Figure 8-57 Control Register 10

7	6	5	4	3	2	1	0
RESERVED			DLYCMP_EN	DLY_TARGET
R-0-0h			R/W-0h	R/W-0h

Table 8-24 Control Register 10 Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R-0	0h	Reserved
4	DLYCMP_EN	R/W	0h	Driver Delay Compensation enable 0h = Disable 1h = Enable
3-0	DLY_TARGET	R/W	0h	Delay Target for Driver Delay Compensation 0h = 0 us 1h = 0.4 us 2h = 0.6 us 3h = 0.8 us 4h = 1 us 5h = 1.2 us 6h = 1.4 us 7h = 1.6 us 8h = 1.8 us 9h = 2 us Ah = 2.2 us Bh = 2.4 us Ch = 2.6 us Dh = 2.8 us Eh = 3 us Fh = 3.2 us