SLVSGI0B september   2022  – july 2023 DRV8411

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
  9. 8 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 External Components
    4. 9.4 Feature Description
      1. 9.4.1 Bridge Control
        1. 9.4.1.1 Parallel Bridge Interface
      2. 9.4.2 Current Regulation
      3. 9.4.3 Protection Circuits
        1. 9.4.3.1 Overcurrent Protection (OCP)
        2. 9.4.3.2 Thermal Shutdown (TSD)
        3. 9.4.3.3 Undervoltage Lockout (UVLO)
    5. 9.5 Device Functional Modes
      1. 9.5.1 Active Mode
      2. 9.5.2 Low-Power Sleep Mode
      3. 9.5.3 Fault Mode
    6. 9.6 Pin Diagrams
      1. 9.6.1 Logic-Level Inputs
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Typical Application
        1. 10.1.1.1 Stepper Motor Application
          1. 10.1.1.1.1 Design Requirements
          2. 10.1.1.1.2 Detailed Design Procedure
            1. 10.1.1.1.2.1 Stepper Motor Speed
            2. 10.1.1.1.2.2 Current Regulation
            3. 10.1.1.1.2.3 Stepping Modes
              1. 10.1.1.1.2.3.1 Full-Stepping Operation
              2. 10.1.1.1.2.3.2 Half-Stepping Operation with Fast Decay
              3. 10.1.1.1.2.3.3 Half-Stepping Operation with Slow Decay
          3. 10.1.1.1.3 Application Curves
        2. 10.1.1.2 Dual BDC Motor Application
          1. 10.1.1.2.1 Design Requirements
          2. 10.1.1.2.2 Detailed Design Procedure
            1. 10.1.1.2.2.1 Motor Voltage
            2. 10.1.1.2.2.2 Current Regulation
            3. 10.1.1.2.2.3 Sense Resistor
          3. 10.1.1.2.3 Application Curves
        3. 10.1.1.3 Thermal Considerations
          1. 10.1.1.3.1 Maximum Output Current
          2. 10.1.1.3.2 Power Dissipation
          3. 10.1.1.3.3 Thermal Performance
            1. 10.1.1.3.3.1 Steady-State Thermal Performance
            2. 10.1.1.3.3.2 Transient Thermal Performance
        4. 10.1.1.4 Multi-Sourcing with Standard Motor Driver Pinout
  12. 11Power Supply Recommendations
    1. 11.1 Bulk Capacitance
    2. 11.2 Power Supply and Logic Sequencing
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|16
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information
10.1.1.3.3 Thermal Performance

The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions.

The data in this section was simulated using the following criteria:

HTSSOP (PWP package)

  • 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the thermal pad (12 vias in 4 x 3 array, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating).
    • Top layer: HTSSOP package footprint and copper plane heatsink. Top layer copper area is varied in simulation.
    • Bottom layer: ground plane thermally connected through vias under the thermal pad for the driver. Bottom layer copper area varies with top copper area.
  • 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the thermal pad (12 vias in 4 x 3 array, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating).
    • Top layer: HTSSOP package footprint and copper plane heatsink. Top layer copper area is varied in simulation.
    • Mid layer 1: GND plane thermally connected to thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm.
    • Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm.
    • Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the package (5 mm x 4.4 mm). Bottom pad size remains constant as top copper plane is varied.

Figure 10-11 shows an example of the simulated board for the HTSSOP package. Table 10-3 shows the dimensions of the board that were varied for each simulation.

GUID-20220906-SS0I-KPNS-V2D4-SSP9GBKB4NZN-low.pngFigure 10-11 HTSSOP PCB model top layer
Table 10-3 Dimension A for 16-pin PWP package
Cu area (cm2)Dimension A (mm)
216.43
422.23
8

30.59

1642.37

WQFN (RTE package)

  • 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating).
    • Top layer: WQFN package footprint and traces.
    • Bottom layer: ground plane thermally connected through vias under the package footprint. Bottom layer copper area is varied in simulation.
  • 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating).
    • Top layer: WQFN package footprint and traces.
    • Mid layer 1: GND plane thermally connected under package footprint through vias. The area of the ground plane is 74.2 mm x 74.2 mm.
    • Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm.
    • Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is 1.55 mm x 1.55 mm. Bottom layer thermal pad is the same size as the package (3 mm x 3 mm). Bottom pad size remains constant.

Figure 10-12 shows an example of the simulated board for the HTSSOP package. Table 10-4 shows the dimensions of the board that were varied for each simulation.

GUID-20220906-SS0I-VRZG-N5LB-N3HMLHW8VSQ7-low.pngFigure 10-12 WQFN PCB model top layer
Table 10-4 Dimension A for 16-pin RTE package
Cu area (cm2)Dimension A (mm)
214.14
420.00
828.28
1640.00