SLVSD29 October   2015 DRV8704

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Motor Drivers
      2. 7.3.2  Direct PWM Input Mode (Dual Brushed DC Gate Driver)
      3. 7.3.3  Current Regulation
      4. 7.3.4  Decay Modes
      5. 7.3.5  Blanking Time
      6. 7.3.6  Gate Drivers
      7. 7.3.7  Configuring Gate Drivers
      8. 7.3.8  External FET Selection
      9. 7.3.9  Protection Circuits
        1. 7.3.9.1 Overcurrent Protection (OCP)
        2. 7.3.9.2 Gate Driver Fault (PDF)
        3. 7.3.9.3 Thermal Shutdown (TSD)
        4. 7.3.9.4 Undervoltage Lockout (UVLO)
      10. 7.3.10 Serial Data Format
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 Control Registers
        1. 7.5.1.1 CTRL Register (Address = 0x00h)
          1. Table 4. CTRL Register
        2. 7.5.1.2 TORQUE Register (Address = 0x01h)
          1. Table 5. TORQUE Register
        3. 7.5.1.3 OFF Register (Address = 0x02h)
          1. Table 6. OFF Register
        4. 7.5.1.4 BLANK Register (Address = 0x03h)
          1. Table 7. BLANK Register
        5. 7.5.1.5 DECAY Register (Address = 0x04h)
          1. Table 8. DECAY Register
        6. 7.5.1.6 Reserved Register Address = 0x05h
          1. Table 9. Reserved Register
        7. 7.5.1.7 DRIVE Register Address = 0x06h
          1. Table 10. DRIVE Register
        8. 7.5.1.8 STATUS Register (Address = 0x07h)
          1. Table 11. STATUS Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 Current Chopping Configuration
        4. 8.2.2.4 Decay Modes
        5. 8.2.2.5 Sense Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TA = 25°C, over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM)
IVM VM operating supply current VM = 24 V 17 22 mA
IVMQ VM sleep mode supply current VM = 24 V, SLEEPn low 65 98 μA
INTERNAL LINEAR REGULATORS (V5, VINT)
V5 V5 output voltage VM ≥ 12 V, IOUT ≤ 10 mA 4.8 5 5.2 V
VINT VINT voltage No external load; reference only 1.7 1.8 1.9 V
LOGIC-LEVEL INPUTS (SLEEPn, AIN1, AIN2, BIN1, BIN2, RESET, SCLK, SDATI, SCS)
VIL Input logic low voltage 0.8 V
VIH Input logic high voltage 1.5 V
VHYS Input logic hysteresis 300 mV
IIL Input logic low current VIN = 0 V –5 5 μA
IIH Input logic high current VIN = 5 V 24 50 70 μA
OPEN DRAIN OUTPUTS (nFAULT, SDATO)
VOL Output logic low voltage IO = 5 mA 0.5 V
IOH Output logic high leakage 10kΩ pullup to 3.3 V –1 1 μA
GATE DRIVERS
VOUTH High-side gate drive output voltage VM = 24 V, IO = 100 μA VM + 10 V
VOUTL Low-side gate drive output voltage VM = 24 V, IO = 100 μA 10 V
tDEAD Output dead time digital delay (dead time is enforced in analog circuits) DTIME = 00 410 ns
DTIME = 01 460
DTIME = 10 670
DTIME = 11 880
IOUT,SRC Peak output sourcing gate drive current IDRIVEP = 00 50 mA
IDRIVEP = 01 100
IDRIVEP = 10 150
IDRIVEP = 11 200
IOUT,SNK Peak output sinking gate drive current IDRIVEN = 00 100 mA
IDRIVEN = 01 150
IDRIVEN = 10 200
IDRIVEN = 11 400
tDRIVE,SRC Peak current drive time for sourcing TDRIVEP = 00 263 ns
TDRIVEP = 01 525
TDRIVEP = 10 1050
TDRIVEP = 11 2100
tDRIVE,SNK Peak current drive time for sinking TDRIVEN = 00 263 ns
TDRIVEN = 01 525
TDRIVEN = 10 1050
TDRIVEN = 11 2100
CURRENT REGULATION
tOFF PWM off time adjustment range Set by TOFF register 0.53 134 μs
tBLANK Current sense blanking time Set by TBLANK register 1.05 7.0 μs
AV Current sense amplifier gain ISGAIN = 00 5 V/V
ISGAIN = 01 10
ISGAIN = 10 20
ISGAIN = 11 40
tSET Settling time (to ±1%) ISGAIN = 00, ∆VIN = 400 mV 150 ns
ISGAIN = 01, ∆VIN = 200 mV 300
ISGAIN = 10, ∆VIN = 100 mV 600
ISGAIN = 11, ∆VIN = 50 mV 1200
VOFS Offset voltage ISGAIN = 00, input shorted 4 mV
VIN Input differential voltage range –600 600 mV
VREF Internal reference voltage 2.50 2.75 3.00 V
PROTECTION CIRCUITS
VUVLO Undervoltage lockout VIN falling; UVLO report 6.3 V
VIN rising; UVLO recovery 7.1 8
VOCP Overcurrent protection trip level (Voltage drop across external FET) OCPTH = 00 160 250 320 mV
OCPTH = 01 380 500 580
OCPTH = 10 620 750 880
OCPTH = 11 840 1000 1200
TTSD(1) Thermal shutdown temperature Die temperature, TJ 150 160 180 °C
THYS(1) Thermal shutdown hysteresis Die temperature, TJ 20 °C
(1) Not tested in production; limits are based on characterization data