SLVSAM9D April 2011 – December 2015 DRV8802
The DRV8802 is an integrated motor driver solution for two brushed DC motors. The device integrates two NMOS H-bridges, current sense, regulation circuitry, and detailed fault detection. The DRV8802 can be powered with a supply voltage from 8.2 V to 45 V and is capable of providing an output current up to 1.6-A full-scale.
A PHASE/ENBL interface allows for simple interfacing to the controller circuit. The winding current control allows the external controller to adjust the regulated current that is provided to the motor. The current regulation is highly configurable, with two decay modes of operation. Fast and slow decay can be selected depending on the application requirements.
A low-power sleep mode is included which allows the system to save power when not driving the motor.
The DRV8802 contains two H-bridge motor drivers with current-control PWM circuitry. Figure 5 shows a block diagram of the motor control circuitry.
Note that there are multiple VM pins. All VM pins must be connected together to the motor supply voltage.
The DRV8802 is fully protected against undervoltage, overcurrent, and overtemperature events.
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge are disabled and the nFAULT pin are driven low. The device remains disabled until either nRESET pin is applied, or VM is removed and re-applied.
Overcurrent conditions on both high and low side devices; that is, a short-to-ground, supply, or across the motor winding results in an overcurrent shutdown. Note that overcurrent protection does not use the current sense circuitry used for PWM current control, and is independent of the ISENSE resistor value or VREF voltage.
If the die temperature exceeds safe limits, all FETs in the H-bridge are disabled and the nFAULT pin are driven low. Once the die temperature has fallen to a safe level operation automatically resumes.
If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the device is disabled and internal logic resets. Operation resumes when VM rises above the UVLO threshold.
The xPHASE input pins control the direction of current flow through each H-bridge, and hence the direction of rotation of a DC motor. The xENBL input pins enable the H-bridge outputs when active high, and can also be used for PWM speed control of the motor. Table 1 shows the logic.
The current through the motor windings is regulated by a fixed-frequency PWM current regulation, or current chopping. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding. Once the current hits the current chopping threshold, the bridge disables the current until the beginning of the next PWM cycle.
For stepping motors, current regulation is normally used at all times, and can changing the current can be used to microstep the motor. For DC motors, current regulation is used to limit the start-up and stall current of the motor.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input from the xVREF pins, and is scaled by a 2-bit DAC that allows current settings of 100%, 71%, 38% of full-scale, plus zero.
The full-scale (100%) chopping current is calculated in Equation 1.
If a 0.5-Ω sense resistor is used and the VREFx pin is 3.3 V, the full-scale (100%) chopping current is 3.3 V / (5 × 0.5 Ω) = 1.32 A.
Two input pins per H-bridge (xI1 and xI0) are used to scale the current in each bridge as a percentage of the full-scale current set by the VREF input pin and sense resistance. The function of the pins is shown in Table 2.
(% FULL-SCALE CHOPPING CURRENT)
|1||1||0% (Bridge disabled)|
Note that when both xI bits are 1, the H-bridge is disabled and no current flows.
If a 0.5-Ω sense resistor is used and the VREF pin is 3.3 V, the chopping current is 1.32 A at the 100% setting (xI1, xI0 = 00). At the 71% setting (xI1, xI0 = 01) the current is 1.32 A × 0.71 = 0.937 A, and at the 38% setting (xI1, xI0 = 10) the current is 1.32 A × 0.38 = 0.502 A. If (xI1, xI0 = 11) the bridge is disabled and no current flows.
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 6 as case 1. The current flow direction shown indicates the state when the xENBL pin is high.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 6 as case 2.
In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is shown in Figure 6 as case 3.
The DRV8802 supports fast decay and slow decay mode. Slow or fast decay mode is selected by the state of the DECAY pin - logic low selects slow decay, and logic high sets fast decay mode. Note that the DECAY pin sets the decay mode for both H-bridges.
DECAY mode also affects the operation of the bridge when it is disabled (by taking the ENBL pin inactive). This applies if the ENABLE input is being used for PWM speed control of the motor, or if it is simply being used to start and stop motor rotation.
If the DECAY pin is high (fast decay), when the bridge is disabled, all FETs are turned off and decay current flows through the body diodes. This allows the motor to coast to a stop.
If the DECAY pin is low (slow decay), both low-side FETs is turned on when ENBL is made inactive. This essentially shorts out the back EMF of the motor, causing the motor to brake, and stop quickly. The low-side FETs stays in the ON state even after the current reaches zero.
After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also sets the minimum on time of the PWM.
The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge drivers. All inputs are ignored while nRESET is active.
Driving nSLEEP low puts the device into a low-power sleep state. In this state, the H-bridges are disabled, the gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time (approximately 1 ms) needs to pass before the motor driver becomes fully operational.