SNLS426F August   2012  – November 2018 DS125BR800

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Description (cont.)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics: Serial Management Bus Interface
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
      2. 8.3.2 PCIe Signal Integrity
        1. 8.3.2.1 RX-Detect in SAS/SATA (up to 6 Gbps) Applications
          1. 8.3.2.1.1 Signal Detect Control for Datarates above 8 Gbps
        2. 8.3.2.2 MODE Operation with SMBus Registers
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBus Mode
    5. 8.5 Programming
      1. 8.5.1 SMBus Master Mode
      2. 8.5.2 Transfer of Data Via the SMBus
      3. 8.5.3 System Management Bus (SMBus) and Configuration Registers
      4. 8.5.4 SMBus Transactions
      5. 8.5.5 Writing a Register
      6. 8.5.6 Reading a Register
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DS125BR800 NJY Package
54-Pin WQFN
Top View
DS125BR800 30201692.gif

Pin Functions(1)

PIN TYPE DESCRIPTION
NAME NO.
DIFFERENTIAL HIGH SPEED I/O'S
INA_0+, INA_0-, INA_1+, INA_1-, INA_2+, INA_2-,INA_3+, INA_3- 10, 11, 12, 13,
15, 16, 17, 18		 I Inverting and noninverting CML differential inputs to the equalizer. On-chip, 50-Ω termination resistor connects INA_n+ to VDD and INA_n- to VDD when enabled.
AC coupling required on high-speed I/O
INB_0+, INB_0-, INB_1+, INB_1-, INB_2+, INB_2-,INB_3+, INB_3-, 1, 2, 3, 4,
5, 6, 7, 8, 		I Inverting and noninverting CML differential inputs to the equalizer. On-chip, 50-Ω termination resistor connects INB_n+ to VDD and INB_n- to VDD when enabled.
AC coupling required on high-speed I/O
OUTA_0+, OUTA_0-, OUTA_1+, OUTA_1-, OUTA_2+, OUTA_2-, OUTA_3+, OUTA_3- 35, 34, 33, 32,
31, 30, 29, 28		 O Inverting and noninverting 50-Ω driver outputs with de-emphasis. Compatible with AC-coupled CML inputs.
AC coupling required on high-speed I/O
OUTB_0+, OUTB_0-, OUTB_1+, OUTB_1-, OUTB_2+, OUTB_2-, OUTB_3+, OUTB_3-, 45, 44, 43, 42,
40, 39, 38, 37		 O Inverting and noninverting 50-Ω driver outputs with de-emphasis. Compatible with AC-coupled CML inputs.
AC coupling required on high-speed I/O
CONTROL PINS — SHARED (LVCMOS)
ENSMB 48 I, 4-LEVEL,
LVCMOS		 System Management Bus (SMBus) Enable pin
Tie 1 kΩ to VDD = Register Access SMBus Slave Mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1 kΩ to GND = Pin Mode
ENSMB = 1 (SMBUS MODE)
AD0-AD3 54, 53, 47, 46 I, 4-LEVEL, LVCMOS ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus slave address inputs.
There are 16 addresses supported by these pins. Pins must be tied LOW or HIGH when used to define the device SMBus address.
READ_EN 26 I, 2-LEVEL, LVCMOS When using an External EEPROM, a transition from high to low starts the load from the external EEPROM
SCL 50 I, 2-LEVEL, LVCMOS,
O, OPEN Drain		 Clock output when loading EEPROM configuration, reverting to SMBus clock input when EEPROM load is complete (ALL_DONE = 0). External 2-kΩ to 5-kΩ pullup resistor to VDD (2.5-V Mode) or VIN (3.3-V Mode) recommended as per SMBus interface standards.
SDA 49 I, 2-LEVEL, LVCMOS,
O, OPEN Drain		 In both SMBus Modes, this pin is the SMBus data I/O. Data input or open-drain output. External 2-kΩ to 5-kΩ pullup resistor to VDD (2.5-V Mode) or VIN (3.3-V Mode) recommended as per SMBus interface standards.
ENSMB = 0 (PIN MODE)
DEMA0, DEMA1,
DEMB0, DEMB1		 49, 50,
53, 54		 I, 4-LEVEL,
LVCMOS		 DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output driver. The pins are only active when ENSMB is de-asserted (low). The 8 channels are organized into two banks. Bank A is controlled with the DEMA[1:0] pins and bank B is controlled with the DEMB[1:0] pins. When ENSMB goes high the SMBus registers provide independent control of each channel. The DEMA[1:0] pins are converted to SMBUS SCL/SDA and DEMB[1:0] pins are converted to AD0, AD1 inputs.
See Table 3.
EQA0, EQA1,
EQB0, EQB1		 20, 19,
46, 47		 I, 4-LEVEL,
LVCMOS		 EQA[1:0] and EQB[1:0] control the level of equalization on the input pins. The pins are active only when ENSMB is deasserted (low). The 8 channels are organized into two banks. Bank A is controlled with the EQA[1:0] pins and bank B is controlled with the EQB[1:0] pins. When ENSMB goes high the SMBus registers provide independent control of each channel. The EQB[1:0] pins are converted to SMBUS AD2/AD3 inputs. See Table 2.
MODE 21 I, 4-LEVEL,
LVCMOS		 MODE control pin selects operating modes.
Tie 1 kΩ to GND = PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6 Gbps)
FLOAT = AUTO Rate Select (for PCIe)
Tie 20 kΩ to GND = PCIe Gen-3 without De-emphasis
Tie 1 kΩ to VDD = PCIe Gen-3 with De-emphasis
See Table 6
SD_TH 26 I, 4-LEVEL,
LVCMOS		 Controls the internal Signal Detect Threshold.
For data rates above 8 Gbps the Signal Detect function should be disabled to avoid potential for intermittent data loss. See Table 5 for additional information.
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
PWDN 52 I, LVCMOS

Tie High = Low power - power down

Tie GND = Normal Operation


See Table 4.
RESERVED 23 I, FLOAT Float (leave pin open) = Normal Operation
RXDET 22 I, 4-LEVEL,
LVCMOS		 The RXDET pin controls the receiver detect function. Depending on the input level, a 50 Ω or >50-kΩ termination to the power rail is enabled.
See Table 4.
VDD_SEL 25 I, LVCMOS Controls the internal regulator
FLOAT = 2.5-V mode
Tie GND = 3.3-V mode
OUTPUTS
ALL_DONE 27 O, LVCMOS Valid Register Load Status Output
HIGH = External EEPROM load failed
LOW = External EEPROM load passed
POWER
GND DAP Power Ground pad (DAP - die attach pad)
VDD 9, 14, 36, 41, 51 Power Power supply pins CML/analog
2.5-V Mode, connect to 2.5-V supply
3.3-V mode, connect 0.1-µF cap to each VDD pin
See Power Supply Recommendations for proper power supply decoupling.
VIN 24 Power In 3.3-V mode, feed 3.3 V to VIN
In 2.5-V mode, leave floating
(1) LVCMOS inputs without the FLOAT conditions must be driven to a logic low or high at all times or operation is not ensured.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3-V Mode operation, VIN pin = 3.3 V and the VDD for the 4-level input is 3.3 V.
For 2.5-V Mode operation, VDD pin = 2.5 V and the VDD for the 4-level input is 2.5 V.