SNLS658 December   2020 DS160PR810

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
        3. 7.5.1.3 SMBus/I 2 C Master Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x16 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Linear Equalization

The DS160PR810 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive channel. Table 7-1 shows available equalization boost through EQ control pins (EQ1_0 and EQ0_0 for channels 0-3 and EQ1_1 and EQ0_1 for channels 4-7), when in Pin Control mode (MODE = L0).

Table 7-1 Equalization Control Settings
EQUALIZATION SETTINGTYPICAL EQ BOOST (dB)
EQ INDEXEQ1_0 (Ch 0-3) / EQ1_1 (Ch 4-7)EQ0_0 (Ch0-3) / EQ0_1 (Ch 4-7)@ 4 GHz@ 8 GHz
0L0L00.0-0.2
1L0L11.54.5
2L0L22.05.5
3L0L32.56.5
4L1L02.77.0
5L1L13.08.0
6L1L24.09.0
7L1L35.010.0
8L2L06.011.0
9L2L17.012.0
10L2L27.513.0
11L2L38.013.5
12L3L08.515.0
13L3L19.516.5
14L3L210.017.0
15L3L311.018.0

The equalization of the device can also be set by writing to SMBus/I2C registers in slave or master mode. Refer to the DS160PR810 Programming Guide (SNLU268) for details.