SNLS714 September   2022 DS320PR822

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Cross Point
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Pin Mode
        1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
        1. 7.5.2.1 Shared Registers
        2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 UPI x24 Lane Cross-Point Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Linear Equalization

The DS320PR822 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive channel. The receivers implement two stage linear equalizer for wide range of equalization capability. The equalizer stages also provide flexibility to make subtle modifications of mid-frequency boost for best EQ gain profile match with wide range of channel media characteristics. The EQ profile control feature is only available in SMBus/I2C mode. In Pin mode the settings are optimized for FR4 traces.

Table 7-1 provides available equalization boost through EQ control pins or SMBus/I2C registers. In Pin Control mode EQ1_0 and EQ0_0 pins set equalization boost for channels 0-3 (Bank 0) and EQ1_1 and EQ0_1 for channels 4-7 (Bank 1). In I2C mode individual channels can be independently programmed for EQ boost.

Table 7-1 Equalization Control Settings
EQUALIZATION SETTING TYPICAL EQ BOOST (dB)
EQ INDEX Pin mode SMBus/I2C Mode at 8 GHz at 16 GHz
EQ1_0/1 EQ0_0/1 eq_stage1_3:0 eq_stage2_2:0 eq_profile_3:0 eq_stage1_bypass
0 L0 L0 0 0 0 1 3.0 4.0
1 L0 L1 1 0 0 1 4.0 6.0
2 L0 L2 3 0 0 1 5.5 8.0
5 L1 L0 0 0 1 0 6.5 10.5
6 L1 L1 1 0 1 0 7.0 11.5
7 L1 L2 2 0 1 0 7.5 12.5
8 L1 L3 3 0 3 0 8.5 13.0
9 L1 L4 4 0 3 0 9.0 14.0
10 L2 L0 5 1 7 0 10.0 15.0
11 L2 L1 6 1 7 0 10.5 15.5
12 L2 L2 8 1 7 0 11.0 16.5
13 L2 L3 10 1 7 0 12.0 17.0
14 L2 L4 10 2 15 0 12.5 18.0
15 L3 L0 11 3 15 0 13.0 19.0
16 L3 L1 12 4 15 0 14.0 19.5
17 L3 L2 13 5 15 0 14.5 20.5
18 L3 L3 14 6 15 0 15.5 21.0
19 L3 L4 15 7 15 0 16.0 22.0