SNLS714 September   2022 DS320PR822

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Cross Point
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Pin Mode
        1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
        1. 7.5.2.1 Shared Registers
        2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 UPI x24 Lane Cross-Point Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.3 Application Curves

The DS320PR822 is a linear redriver that can be used to extend channel reach of a PCIe link. Normally, PCIe-compliant Tx and Rx are equipped with signal-conditioning functions and can handle channel losses of up to 36 dB at 16 GHz. With the DS320PR822, the total channel loss between a PCIe root complex and an end point can be extended up to 58 dB at 16 GHz.

To demonstrate the reach extension capability of the DS320PR822, two comparative setups are constructed. In first setup as shown in Figure 8-3 there is no redriver in the PCIe 5.0 link. Figure 8-4 shows eye diagram at the end of the link using SigTest. In second setup as shown in Figure 8-5, the DS320PR822 is inserted in the middle to extend link reach. Figure 8-6 shows SigTest eye diagram.

Figure 8-3 PCIe 5.0 Link Baseline Setup Without Redriver the Link Elements
Figure 8-5 PCIe 5.0 Link Setup with the DS320PR822 the Link Elements
GUID-20220329-SS0I-1HDN-TV23-HBT3D46GCVVW-low.pngFigure 8-4 PCIe 5.0 link Baseline Setup Without Redriver Eye Diagram Using SigTest
GUID-20220329-SS0I-QSKR-MJXT-XG7Z7MKC9BR2-low.pngFigure 8-6 PCIe 5.0 Link Setup with the DS320PR822 Eye Diagram Using SigTest

Table 8-1 provides the PCIe 5.0 links without and with the DS320PR822. The illustration shows that redriver is capable of ≅22 dB reach extension at PCIe 5.0 speed with EQ = 10 (EQ gain of 16 dB) and GAIN1,2 = L1 (flat gain of −4 dB). Note: actual reach extension depends on various signal integrity factors. It is recommended to run signal intergrity simulations with all the components in the link to get any guidance.

Table 8-1 PCIe 5.0 Reach Extension using the DS320PR822
Setup Pre Channel Loss Post Channel Loss Total Loss Eye at BER 1E-12 SigTest Pass?
Baseline – no DUT — — ≅36 dB 14 ps, 41 mV Pass
With DUT (DS320PR822) ≅29 dB ≅29 dB ≅58 dB 14 ps, 33 mV Pass