SNLS714 September   2022 DS320PR822

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Cross Point
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Pin Mode
        1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
        1. 7.5.2.1 Shared Registers
        2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 UPI x24 Lane Cross-Point Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.2 Detailed Design Procedure

For UPI operation, DS320PR822 is designed with linear data-path to pass the Tx Preset signaling (by CPUs) onto the Rx (of CPUs) for link training to optimize the equalization settings. The linear redriver DS320PR822 helps extend the PCB trace reach distance by boosting the attenuated signals with its equalization, which allows the user to recover the signal by the downstream Rx more easily. The DS320PR822 must be placed in between the CPU Tx and CPU Rx in such a way that signal swing at the device output pins for both Rx and Tx stays within the linearity range of the device. Adjustments to the DS320PR822 EQ setting should be performed based on the channel loss to optimize the eye opening in the Rx partner. The available EQ gain settings are provided in Table 7-1. For most systems the default flat gain setting 0 dB (GAIN = floating) would be sufficient. However, a flat gain attenuation can be utilized to apply extra equalization when needed to keep the data-path linear.

The DS320PR822 can be optimized for a given system utilizing its three configuration modes – Pin mode, SMBus/I2C Primary mode, and SMBus/I2C Secondary mode. In SMBus/I2C modes the SCL and SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7 kΩ is a good first approximation for a bus capacitance of 10 pF.

Figure 8-2 shows a simplified schematic for x24 lane configuration in SMBus/I2C Primary mode.

GUID-20210507-CA0I-08R1-SVQK-FFF1NZ2GRNCT-low.gif Figure 8-2 Simplified Schematic for UPI x24 Lane Configuration in SMBus/I2C Primary Mode