9.2.1 Design Requirements

In a typical design, the DS40MB200 equalizes a short backplane trace on its input, followed by a longer trace at the DS40MB200 output. In this application example, a 25-inch FR4 coupled micro-strip board trace is used in place of the short backplane link. A block diagram of this example is shown in Figure 11.

Figure 11. Block Diagram of DS40MB200 Application Example

The 25-inch microstrip board trace has approximately 6 dB of attenuation between 375 MHz and 1.875 GHz, representing closely the transmission loss of the short backplane transmission line. The 25-inch microstrip is connected between the pattern generator and the differential inputs of the DS40MB200 for AC measurements.

The length of the output trace may vary based on system requirements. In this example, a 40-inch FR4 trace with similar trace width, separation, and dielectric characteristics is placed at the DS40MB200 output.

As with any high-speed design, there are many factors which influence the overall performance. Following is a list of critical areas for consideration and study during design.

• Use 100-Ω impedance traces. Generally, these are very loosely coupled to ease routing length differences.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• The maximum body size for AC-coupling capacitors is 0402.
• Back-drill connector vias and signal vias to minimize stub length.
• Use reference plane vias to ensure a low inductance path for the return current.

9.2.2 Detailed Design Procedure

For optimal design, the DS40MB200 must be configured to route incoming data correctly as well as to provide the best signal quality. The following design procedures must be observed:

1. The DS40MB200 must be configured to provide the correct multiplexer and buffer routes in order to satisfy system requirements. In order to set the appropriate multiplexer control settings, refer to Table 1. To configure the buffer control settings, refer to Table 2. For example, consider the case where the designer wishes to route the input from Switch Card A (SIA0_0±) to the output for the line card (LO_0±). To accomplish this, set MUX_S0 = 1 (select SIA0_0±). For the other direction from line card output to switch card, set LB0A = 1 and LB0B = 1 so that the input from the line-card is buffered to both Switch Card A (SOA_0±) and Switch Card B (SOB_0±).
2. The DS40MB200 is designed to be placed at an offset location with respect to the overall channel attenuation. To optimize performance, the multiplexer buffer transmit pre-emphasis can be tuned to extend the trace length reach while also recovering a solid eye opening. To tune transmit pre-emphasis on either the line card side or switch card side, refer to Table 3 and Table 4 for recommended pre-emphasis control settings according to the length of FR4 board trace connected at the DS40MB200 output. For example, if 40 inches of FR4 trace is connected to the switch card output, set PreS_[1:0] = (1, 1) for VOD = 1200 mVpp and –9 dB of transmit pre-emphasis.

9.2.3 Application Curves

Figure 12 through Figure 17 show how the signal integrity varies at different places in the data path. These measured locations can be referenced back to the labeled points provided in Figure 11.

• Point (A): Output signal of source pattern generator
• Point (B): Input to DS40MB200 after 25 inches of FR4 trace from source
• Point (C): Output of DS40MB200 driver
• Point (D): Signal after 40 inches of FR4 trace from DS40MB200 driver

The source signal is a PRBS-7 pattern at 4 Gbps. For the long output traces, the eye after 40 inches of output FR4 trace is significantly improved by adding –9 dB of pre-emphasis.

Figure 12. Eye Measured at Point (A)

Figure 14. Eye Measured at Point (C), Pre-Emph = 0 dB

Figure 16. Eye Measured at Point (C), Pre-Emph = –9 dB

Figure 13. Eye Measured at Point (B)

Figure 15. Eye Measured at Point (D), Pre-Emph = 0 dB

Figure 17. Eye Measured at Point (D), Pre-Emph = –9 dB