SNLS144J June   2005  – January 2016 DS40MB200

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CML Inputs and EQ
      2. 8.3.2 Multiplexer and Loopback Control
      3. 8.3.3 CML Drivers and Pre-Emphasis Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The DS40MB200 is a signal conditioning 2:1 multiplexer and 1:2 buffer designed to support port redundancy with encoded or scrambled data rates between 1 and 4 Gbps. The DS40MB200 provides fixed equalization at the receive input and pre-emphasis control on the output in order to support signal reach extension.

8.2 Functional Block Diagram

DS40MB200 20021731.gif

8.3 Feature Description

The DS40MB200 MUX buffer consists of several key blocks:

  • CML Inputs and EQ
  • Multiplexer and Loopback Control
  • CML Drivers and Pre-Emphasis Control

8.3.1 CML Inputs and EQ

The high-speed inputs are self-biased to about 1.3 V at IN+ and IN- and are designed for AC coupling. See Figure 7 for details about the internal receiver input termination and bias circuit.

DS40MB200 20021750.gif Figure 7. Receiver Input Termination and Bias Circuit

The inputs are compatible to most AC coupling differential signals such as LVDS, LVPECL, and CML. The DS40MB200 is not designed to operate with data rates below 1000 Mbps or with a DC bias applied to the CML inputs or outputs. Most high-speed links are encoded for DC balance and have been defined to include AC coupling capacitors, allowing the DS40MB200 to be inserted directly into the datapath without any limitation. The ideal AC-coupling capacitor value is often based on the lowest frequency component embedded within the serial link. A typical AC-coupling capacitor value ranges between 100 and 1000 nF. Some specifications with scrambled data may require a larger capacitor for optimal performance. To reduce unwanted parasitic effects around and within the AC-coupling capacitor, a body size of 0402 is recommended. Figure 6 shows the AC-coupling capacitor placement in an AC test circuit.

Each input stage has a fixed equalizer that provides equalization to compensate about 5 dB (at 2 GHz) of transmission loss from a short backplane trace (about 10 inches backplane).

8.3.2 Multiplexer and Loopback Control

Table 1 and Table 2 provide details about how to configure the DS40MB200 multiplexer and loopback settings.

Table 1. Logic Table for Multiplex Controls

PIN PIN VALUE MUX FUNCTION
MUX_S0 0 MUX_0 select switch_B input, SIB_0±.
1 (default) MUX_0 select switch_A input, SIA_0±.
MUX_S1 0 MUX_1 select switch_B input, SIB_1±.
1 (default) MUX_1 select switch_A input, SIA_0±.

Table 2. Logic Table for Loopback Controls

PIN PIN VALUE LOOPBACK FUNCTION
LB0A 0 Enable loopback from SIA_0± to SOA_0±.
1 (default) Normal mode. Loopback disabled.
LB0B 0 Enable loopback from SIB_0± to SOB_0±.
1 (default) Normal mode. Loopback disabled.
LB1A 0 Enable loopback from SIA_1± to SOA_1±.
1 (default) Normal mode. Loopback disabled.
LB1B 0 Enable loopback from SIB_1± to SOB_1±.
1 (default) Normal mode. Loopback disabled.

8.3.3 CML Drivers and Pre-Emphasis Control

The output driver has pre-emphasis (driver-side equalization) to compensate the transmission loss of the backplane that it is driving. The driver conditions the output signal such that the lower frequency and higher frequency pulses reach approximately the same amplitude at the end of the backplane and minimize the deterministic jitter caused by the amplitude disparity. The DS40MB200 provides four steps of user-selectable pre-emphasis ranging from 0, –3, –6 and –9 dB to handle different lengths of backplane. Figure 8 shows a driver pre-emphasis waveform. The pre-emphasis duration is 200 ps nominal, corresponding to 0.8 unit intervals (UI) at 4Gbps. The pre-emphasis levels of switch-side and line-side can be individually programmed.

DS40MB200 20021737.gif Figure 8. Driver Pre-Emphasis Differential Waveform (Showing All 4 Pre-Emphasis Steps)

Table 3. Line-Side Pre-Emphasis Controls

PreL_[1:0] PRE-EMPHASIS LEVEL IN mVPP
(VODB)		 DE-EMPHASIS LEVEL IN mVPP
(VODPE)		 PRE-EMPHASIS IN dB
(VODPE/VODB)		 TYPICAL FR4
BOARD TRACE
0 0 1200 1200 0 10 inches
0 1 1200 850 −3 20 inches
1 0 1200 600 −6 30 inches
1 1
(default)		 1200 426 −9 40 inches

Table 4. Switch-Side Pre-Emphasis Controls

PreS_[1:0] PRE-EMPHASIS LEVEL IN mVPP
(VODB)		 DE-EMPHASIS LEVEL IN mVPP
(VODPE)		 PRE-EMPHASIS IN dB
(VODPE/VODB)		 TYPICAL FR4
BOARD TRACE
0 0 1200 1200 0 10 inches
0 1 1200 850 −3 20 inches
1 0 1200 600 −6 30 inches
1 1
(default)		 1200 426 −9 40 inches