SNLS144J June   2005  – January 2016 DS40MB200

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CML Inputs and EQ
      2. 8.3.2 Multiplexer and Loopback Control
      3. 8.3.3 CML Drivers and Pre-Emphasis Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Use at least a four-layer board with a power and ground plane. Closely coupled differential lines of 100 Ω are typically recommended for differential interconnect. The closely coupled lines help to ensure that coupled noise will appear as common-mode and thus will be rejected by the receivers. Information on the WQFN style package is provided in AN-1187 Leadless Leadframe Package (LLP) (SNOA401).

11.2 Layout Examples

Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Figure 18. A layout example for the DS40MB200 DAP is shown in Figure 19, where 16 stencil openings are used for the DAP alongside nine vias to GND.

DS40MB200 stencil_wqfn_dpi_v2.png Figure 18. No Pullback WQFN, Single Row Reference Diagram

Table 6. No Pullback WQFN Stencil Aperture Summary for DS40MB200

DEVICE PIN COUNT MKT DWG PCB I/O PAD SIZE (mm) PCB PITCH (mm) PCB DAP SIZE (mm) STENCIL I/O APERTURE (mm) STENCIL DAP APERTURE (mm) NUMBER
OF DAP
APERTURE OPENINGS		 GAP BETWEEN DAP APERTURE
(Dim A mm)
DS40MB200 48 SQA48A 0.25 × 0.6 0.5 5.1 × 5.1 0.25 × 0.7 1.1 × 1.1 16 0.2
DS40MB200 wqfn-48_layout.gif Figure 19. 48-Pin WQFN Stencil Example of Via and Opening Placement