SNLS493A October   2014  – January 2015 DS80PCI810

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Handling Ratings
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Electrical Characteristics — Serial Management Bus Interface
    8. 6.8 Timing Requirements Serial Bus Interface
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1
      2. 7.2.2 Functional Datapath Blocks
    3. 7.3 Feature Description
      1. 7.3.1 Typical 4-Level Input Thresholds
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pin Control Mode:
      2. 7.4.2 Slave SMBus Mode:
      3. 7.4.3 SMBus Master Mode
      4. 7.4.4 Signal Conditioning Settings
    5. 7.5 Programming
      1. 7.5.1 EEPROM Address Map for Single Device
      2. 7.5.2 SMBus
      3. 7.5.3 Transfer Of Data Via The SMBus
      4. 7.5.4 SMBus Transactions
    6. 7.6 Writing a Register
    7. 7.7 Reading a Register
    8. 7.8 Register Maps
  8. Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 DS80PCI810 versus DS80PCI800
      2. 8.1.2 Signal Integrity in PCIe Applications
      3. 8.1.3 Rx Detect Functionality in PCIe Applications
    2. 8.2 Typical Applications
      1. 8.2.1 Generic High Speed Repeater
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
          1. 8.2.1.3.1 Pre-Channel Only Setup
          2. 8.2.1.3.2 Pre-Channel and Post-Channel Setup
      2. 8.2.2 PCIe Board Applications (PCIe Gen-3)
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Design Procedure
        3. 8.2.2.3 Application Performance Plots
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Low 70 mW/Channel (Typ) Power Consumption, With Option to Power Down Unused Channels
  • Seamless Link Training Support
  • Advanced Configurable Signal Conditioning I/O
    • Receive CTLE up to ~10 dB at 4 GHz
    • Linear Output Driver
    • Variable Output Voltage Range up to 1200 mVp-p
  • Automatic Receiver Detect (Hot-Plug)
  • Ultra-Low Input-to-Output Latency: 80 ps (Typ)
  • Programmable via Pin Selection, EEPROM, or SMBus Interface
  • Single Supply Voltage: 2.5 V or 3.3 V
  • 4 kV HBM ESD Rating
  • −40°C to 85°C Operating Temperature Range
  • Flow-Thru Layout in 10 mm x 5.5 mm 54-Pin Leadless WQFN Package
  • Pin Compatible with DS80PCI800

2 Applications

  • PCI Express Gen-1, 2, and 3
  • Other Proprietary High Speed Interfaces Up to 8 Gbps

Simplified Functional Block Diagram

simplified_schematic.gif

3 Description

The DS80PCI810 is an extremely low-power high-performance repeater/redriver designed to support eight channels carrying high speed interface up to 8 Gbps, such as PCIe Gen-1, 2, and 3. The receiver's continuous time linear equalizer (CTLE) provides high frequency boost that is programmable from 2.7 to 9.5 dB at 4 GHz (8 Gbps) followed by a linear output driver. The CTLE receiver is capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as board traces or twin axial-copper cables. The programmable equalization maximizes the flexibility of physical placement within the interconnect channel and improves overall channel performance.

When operating in PCIe applications, the DS80PCI810 preserves transmit signal characteristics, thereby allowing the host controller and the end point to negotiate transmit equalizer coefficients. This transparency in the link training protocol facilitates system level interoperability and minimizes latency.

The programmable settings can be applied easily via pin control, software (SMBus or I2C), or direct loading from an external EEPROM. In EEPROM mode, the configuration information is automatically loaded on power up, thereby eliminating the need for an external microprocessor or software driver.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS80PCI810 WQFN (54) 10 mm x 5.5 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Typical Application Block Diagram

PCIe_Typical_Diagram.gif