SNLS337M October   2010  – August 2017 DS90UH926Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC and AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing Requirements for the Serial Control Bus
    9. 6.9  Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  Backward Compatible Mode
      4. 7.3.4  Input Equalization Gain
      5. 7.3.5  Common-Mode Filter Pin (CMF)
      6. 7.3.6  Video Control Signal Filter
      7. 7.3.7  EMI Reduction Features
        1. 7.3.7.1 Spread Spectrum Clock Generation (SSCG)
      8. 7.3.8  Enhanced Progressive Turnon (EPTO)
      9. 7.3.9  LVCMOS VDDIO Option
      10. 7.3.10 Power Down (PDB)
      11. 7.3.11 Stop Stream Sleep
      12. 7.3.12 Serial Link Fault Detect
      13. 7.3.13 Oscillator Output
      14. 7.3.14 Pixel Clock Edge Select (RFB)
      15. 7.3.15 Built In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
          1. 7.3.15.1.1 Sample BIST Sequence
        2. 7.3.15.2 Forward-Channel and Back-Channel Error Checking
      16. 7.3.16 Image Enhancement Features
        1. 7.3.16.1 White Balance
          1. 7.3.16.1.1 LUT Contents
          2. 7.3.16.1.2 Enabling White Balance
        2. 7.3.16.2 Adaptive HI-FRC Dithering
      17. 7.3.17 Internal Pattern Generation
      18. 7.3.18 I2S Receiving
        1. 7.3.18.1 I2S Jitter Cleaning
        2. 7.3.18.2 Secondary I2S Channel
          1. 7.3.18.2.1 MCLK
      19. 7.3.19 Interrupt Pin: Functional Description and Usage (INTB)
      20. 7.3.20 GPIO[3:0] and GPO_REG[8:4]
        1. 7.3.20.1 GPIO[3:0] Enable Sequence
        2. 7.3.20.2 GPO_REG[8:4] Enable Sequence
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN), and Output State Select (OSS_SEL)
      2. 7.4.2 Low Frequency Optimization (LFMODE)
      3. 7.4.3 Configuration Select (MODE_SEL)
      4. 7.4.4 HDCP Repeater
        1. 7.4.4.1 Repeater Connections
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Display Application
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Transmission Media
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CML Interconnect Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from L Revision (February 2017) to M Revision

  • Reverted all previous MLCK content changes made in Revision L back to Revision KGo
  • Removed disable jitter cleaner noteGo

Changes from K Revision (January 2015) to L Revision

  • Changed top view pin out diagram Go
  • Changed CLK to RES2 Go
  • Added note to disable jitter cleaner Go
  • Changed MCLK to RES2 Go
  • Deleted reference to MCLK in this section Go
  • Deleted reference to MCLK in this section Go
  • Deleted reference to MCLK Go
  • Deleted I2S Jitter Cleaning section Go
  • Deleted MCLK section Go
  • Deleted MCLK columns in the Audio Interface Frequencies tableGo
  • Changed values in columns 2 to 5 of Configuration Select (MODE_SEL) tableGo
  • Changed values in columns 2 to 5 of IDx table Go
  • Changed Removed register reference to MCLKGo
  • Changed Typical Display System Diagram (removed MCLK) Go
  • Changed Power-Up Requirements and PDB pin description and added Power-Up Sequence graphic. Go

Changes from J Revision (April 2013) to K Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from I Revision (August 2012) to J Revision

  • Changed layout of National Semiconductor data sheet to TI formatGo

Changes from H Revision (March 2012) to I Revision

  • : Configuration Select (MODE_SEL) #6 I2S Channel B (18–bit Mode) from L to H, corrected typo in table “DC and AC Serial Control Bus Characteristics” from VDDIO to VDD33, added Recommended FRC settings table, added “When backward compatible mode = ON, set LFMODE = 0” under Functional Description. Reformatted table 9 and added clarification to notes. Added clarification to notes on Serial Control Bus Registers, address 0x02[3:0] (backwards compatible and LFMODE registers), added “Note: Do not enable SSCG feature if PCLK source into the SER has an SSC clock already.” under Functional Description, EMI REDUCTION FEATURES, Spread Spectrum Clock Generation (SSCG)Go

Changes from G Revision (February 2012) to H Revision

  • Deleted “DC Electrical Characteristics” PDB VDDIO = 1.71 to 1.89 V, added under “SUPPLY CURRENT IDDZ, DDIOZ, IDDIOZMax = 10 mA, added under “CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS” EW Min = 0.3 UI AND EH Min = 200 mV, added “INTERRUPT PIN — FUNCTIONAL DESCRIPTION AND USAGE (INTB)” under Functional Description section, updated "POWER DOWN (PDB) description under Functional Description from VDDIO to VDDIO = 3 to 3.6 V or VDD33, updated Figure 24 Go