SNLS321C May   2010  – May 2016 DS92LV2421 , DS92LV2422

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Serializer DC
    6. 6.6  Electrical Characteristics - Deserializer DC
    7. 6.7  Electrical Characteristics - DC and AC Serial Control Bus
    8. 6.8  Timing Requirements - DC and AC Serial Control Bus
    9. 6.9  Timing Requirements - Serializer for CLKIN
    10. 6.10 Timing Requirements - Serial Control Bus
    11. 6.11 Switching Characteristics - Serializer
    12. 6.12 Switching Characteristics - Deserializer
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Data Transfer
      2. 7.3.2 Video Control Signal Filter - Serializer and Deserializer
      3. 7.3.3 Serializer Functional Description
        1. 7.3.3.1 EMI Reduction Features
          1. 7.3.3.1.1 Data Randomization and Scrambling
          2. 7.3.3.1.2 Serializer Spread Spectrum Compatibility
        2. 7.3.3.2 Signal Quality Enhancers
          1. 7.3.3.2.1 Serializer VOD Select (VODSEL)
          2. 7.3.3.2.2 Serializer De-Emphasis (De-Emph)
        3. 7.3.3.3 Power-Saving Features
          1. 7.3.3.3.1 Serializer Power-Down Feature (PDB)
          2. 7.3.3.3.2 Serializer Stop Clock Feature
          3. 7.3.3.3.3 1.8-V or 3.3-V VDDIO Operation
          4. 7.3.3.3.4 Deserializer Power-Down Feature (PDB)
          5. 7.3.3.3.5 Deserializer Stop Stream SLEEP Feature
        4. 7.3.3.4 Serializer Pixel Clock Edge Select (RFB)
        5. 7.3.3.5 Optional Serial Bus Control
        6. 7.3.3.6 Optional BIST Mode
      4. 7.3.4 Deserializer Functional Description
        1. 7.3.4.1  Signal Quality Enhancers
          1. 7.3.4.1.1 Deserializer Input Equalizer Gain (EQ)
        2. 7.3.4.2  EMI Reduction Features
          1. 7.3.4.2.1 Deserializer Output Slew Rate Select (OS_CLKOUT/OS_DATA)
          2. 7.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) (Optional)
          3. 7.3.4.2.3 Deserializer SSCG Generation (Optional)
          4. 7.3.4.2.4 1.8-V or 3.3-V VDDIO Operation
        3. 7.3.4.3  Deserializer Clock-Data Recovery Status Flag (LOCK) And Output State Select (OSS_SEL)
        4. 7.3.4.4  Deserializer Oscillator Output (Optional)
        5. 7.3.4.5  Deserializer OP_LOW (Optional)
        6. 7.3.4.6  Deserializer Clock Edge Select (RFB)
        7. 7.3.4.7  Deserializer Control Signal Filter (Optional)
        8. 7.3.4.8  Deserializer Low Frequency Optimization (LF_Mode)
        9. 7.3.4.9  Deserializer Map Select
        10. 7.3.4.10 Deserializer Strap Input Pins
        11. 7.3.4.11 Optional Serial Bus Control
        12. 7.3.4.12 Optional BIST Mode
      5. 7.3.5 Built-In Self Test (BIST)
        1. 7.3.5.1 Sample BIST Sequence
        2. 7.3.5.2 BER Calculations
      6. 7.3.6 Optional Serial Bus Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serializer and Deserializer Operating Modes and Reverse Compatibility (CONFIG[1:0])
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Display Application
      2. 8.1.2 Live Link Insertion
      3. 8.1.3 Alternate Color / Data Mapping
    2. 8.2 Typical Applications
      1. 8.2.1 DS92LV2421 Typical Connection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 DS92LV2422 Typical Connection
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 WQFN (LLP) Stencil Guidelines
      2. 10.1.2 Transmission Media
      3. 10.1.3 LVDS Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resource
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN MAX UNIT
Supply voltage, VDDn (1.8 V) –0.3 2.5 V
Supply voltage, VDDIO –0.3 4 V
LVCMOS I/O voltage –0.3 VDDIO + 0.3 V
Receiver input voltage –0.3 VDD + 0.3 V
Driver output voltage –0.3 VDD + 0.3 V
48L RHS package Maximum power dissipation capacity at 25°C 225 mW
Derate above 25°C 1 / RθJA mW/°C
60L NKB package Maximum power dissipation capacity at 25°C 525 mW
Derate above 25°C 1 / RθJA mW/°C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
(3) For soldering specifications, see product folder at www.ti.com and SNOA549.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±8000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
Machine model (MM) ±250
IEC 61000-4-2 contact discharge DOUT+, DOUT- ≥±8000
RIN+, RIN- ≥±8000
IEC 61000-4-2 air-gap discharge DOUT+, DOUT- ≥±25000
RIN+, RIN- ≥±25000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDDn Supply voltage 1.71 1.8 1.89 V
VDDIO LVCMOS supply voltage 1.71 1.8 1.89 V
VDDIO LVCMOS supply voltage 3 3.3 3.6 V
Clock frequency 10 75 MHz
Supply noise(1) 50 mVp-p
TA Operating free-air temperature –40 25 85 °C
(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDDn (1.8 V) supply with amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the serializer and output of the deserializer with 10 meter cable shows no error when the noise frequency on the serializer is less than 750 kHz. The deserializer, on the other hand, shows no error when the noise frequency is less than 400 kHz.

6.4 Thermal Information

Over operating free-air temperature range (unless otherwise noted)
THERMAL METRIC(1) DS92LV2421 DS92LV2422 UNIT
RHS (WQFN) NKB (WQFN)
48 PINS 60 PINS
RθJA Junction-to-ambient thermal resistance(2) 30.3 26.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(2) 11.5 9.1 °C/W
RθJB Junction-to-board thermal resistance 7.3 6 °C/W
ψJT Junction-to-top characterization parameter 0.1 0.1 °C/W
ψJB Junction-to-board characterization parameter 7.3 6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.7 1.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) Based on nine thermal vias.

6.5 Electrical Characteristics – Serializer DC

Over recommended operating supply and temperature ranges (unless otherwise noted).(1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVCMOS INPUT DC SPECIFICATIONS
VIH High level input voltage VDDIO = 3 V to 3.6 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) 2.2 VDDIO V
VDDIO = 1.71 V to 1.89 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) 0.65 × VDDIO VDDIO
VIL Low level input voltage VDDIO = 3 V to 3.6 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) GND 0.8 V
VDDIO = 1.71 V to 1.89 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) GND 0.35 × VDDIO
IIN Input current VIN = 0 V or VDDIO (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) VDDIO = 3 V to 3.6 V –15 ±1 15 μA
VDDIO = 1.7 V to 1.89 V –15 ±1 15
CML DRIVER DC SPECIFICATIONS
VOD Differential output voltage RL = 100 Ω, de-emphasis = disabled (see Figure 2; DOUT+ and DOUT– pins) VODSEL = 0 ±205 ±280 ±355 mV
VODSEL = 1 ±320 ±420 ±520
VODp-p Differential output voltage
(DOUT+) – (DOUT-)		 RL = 100 Ω, de-emphasis = disabled (see Figure 2; DOUT+ and DOUT– pins) VODSEL = 0 560 mVp-p
VODSEL = 1 840
ΔVOD Output voltage unbalance RL = 100 Ω, de-emphasis = disabled, VODSEL = L (DOUT+ and DOUT– pins) 1 50 mV
VOS Offset voltage
(single-ended) 		At TP A and B (see Figure 1), RL = 100 Ω, de-emphasis = disabled (DOUT+ and DOUT– pins) VODSEL = 0 1.65 V
VODSEL = 1 1.575
ΔVOS Offset voltage unbalance
(single-ended)		 At TP A and B (see Figure 1), RL = 100 Ω,
de-emphasis = disabled (DOUT+ and DOUT– pins)		 1 mV
IOS Output short circuit current DOUT± = 0 V, de-emphasis = disabled,
VODSEL = 0 (DOUT+ and DOUT– pins)		 –36 mA
RTO Internal output termination resistor DOUT+ and DOUT– pins 80 100 120 Ω
SUPPLY CURRENT
IDDT1 Serializer supply current
(includes load current)		 RL = 100 Ω, CLKIN = 75 MHz, checker board pattern,
de-emphasis = 3 kΩ, VODSEL = H
(see Figure 9)		 VDD = 1.89 V 75 90 mA
VDDIO = 1.89 V 3 5
IDDIOT1 VDDIO = 3.6 V 11 15
IDDT2 Serializer supply current
(includes load current)		 RL = 100 Ω, CLKIN = 75 MHz, checker board pattern,
de-emphasis = 6 kΩ, VODSEL = L
(see Figure 9)		 VDD = 1.89 V 65 80 mA
VDDIO = 1.89 V 3 5
IDDIOT2 VDDIO = 3.6 V 11 15
IDDZ Serializer supply current power-down PDB = 0 V, All other LVCMOS Inputs = 0 V VDD = 1.89 V 40 1000 µA
VDDIO = 1.89 V 5 10
IDDIOZ VDDIO = 3.6 V 10 20
(1) The electrical characteristics tables list verified specifications under the listed recommended operating conditions except as otherwise modified or specified by the electrical characteristics conditions or notes. Typical specifications are estimations only and are not verified.
(2) Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25°C, and at the recommended operation conditions at the time of product characterization and are not verified.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH, and VTL, which are differential voltages.

6.6 Electrical Characteristics – Deserializer DC

Over recommended operating supply and temperature ranges (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
3.3-V I/O LVCMOS DC SPECIFICATIONS (VDDIO = 3 V TO 3.6 V)
VIH High level input voltage PDB and BISTEN pins 2.2 VDDIO V
VIL Low level input voltage PDB and BISTEN pins GND 0.8 V
IIN Input current VIN = 0 V or VDDIO (PDB and BISTEN pins) −15 ±1 15 μA
VOH High level output voltage IOH = −2 mA, OS_CLKOUT/DATA = L (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins) 2.4 VDDIO V
VOL Low level output voltage IOL = 3 mA, OS_CLKOUT/DATA = L (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins) GND 0.4 V
IOS Output short circuit current VDDIO = 3.3 V, VOUT = 0 V, OS_CLKOUT/DATA = L/H (CLKOUT pin) 36 mA
Output short circuit current VDDIO = 3.3 V, VOUT = 0 V, OS_CLKOUT/DATA = L/H (output pins) 37
IOZ TRI-STATE output current PDB = 0 V, OSS_SEL = 0 V, VOUT = H (output pins) −15 15 µA
1.8-V I/O LVCMOS DC SPECIFICATIONS (VDDIO = 1.71 V to 1.89 V)
VIH High level input voltage PDB and BISTEN pins 1.235 VDDIO V
VIL Low level input voltage PDB and BISTEN pins GND 0.595 V
IIN Input current VIN = 0 V or VDDIO (PDB and BISTEN pins) −15 ±1 15 μA
VOH High level output voltage IOH = –2 mA, OS_CLKOUT/DATA = L/H (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins) VDDIO – 0.45 VDDIO V
VOL Low level output voltage IOL = 2 mA, OS_CLKOUT/DATA = L/H (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins) GND 0.45 V
IOS Output short circuit current VDDIO = 1.8 V, VOUT = 0 V, OS_CLKOUT/DATA = L/H (CLKOUT pin) 18 mA
Output short circuit current VDDIO = 1.8 V, VOUT = 0 V, OS_CLKOUT/DATA = L/H (output pins) 18
IOZ TRI-STATE output current PDB = 0 V, OSS_SEL = 0 V, VOUT = 0 V or VDDIO (output pins) –15 15 µA
CML RECEIVER DC SPECIFICATIONS
VTH Differential input threshold high voltage VCM = 1.2 V, RIN+ and RIN- pins (Internal VBIAS) 50 mV
VTL Differential input threshold low voltage VCM = 1.2 V, RIN+ and RIN- pins (Internal VBIAS) –50 mV
VCM Common mode voltage RIN+ and RIN- pins (Internal VBIAS) 1.2 V
IIN Input current VIN = 0 V or VDDIO, RIN+ and RIN- pins –15 15 µA
RTI Internal input termination resistor RIN+ and RIN- pins 80 100 120 Ω
LOOP THROUGH CML DRIVER OUTPUT DC SPECIFICATIONS (EQ TEST PORT(1))
VOD Differential output voltage ROUT+ and ROUT- pins, RL = 100 Ω 542 mV
VOS Offset voltage
(single-ended)		 ROUT+ and ROUT- pins, RL = 100 Ω 1.4 V
RT Internal termination resistor ROUT+ and ROUT- pins 80 100 120 Ω
SUPPLY CURRENT
IDD1 Deserializer supply current (includes load current) CLKOUT = 75 MHz, checker board pattern, OS_CLKOUT/DATA = H,
CL = 4 pF (see Figure 9)		 VDD = 1.89 V 97 115 mA
IDDIO1 VDDIO = 1.89 V 40 50
VDDIO = 3.6 V 75 85
IDDZ Deserializer supply current power down PDB = 0 V, All other LVCMOS Inputs = 0 V VDD = 1.89 V 100 3000 µA
VDDIO = 1.89 V 6 50
IDDIOZ VDDIO = 3.6 V 12 100
(1) Specification is verified by characterization and is not tested in production.

6.7 Electrical Characteristics – DC and AC Serial Control Bus

Over 3.3-V supply and temperature ranges (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input high level SDA and SCL 2.2 VDDIO V
VIL Input low level voltage SDA and SCL GND 0.8 V
VHY Input hysteresis >50 mV
VOL Output low level voltage(1) SDA, IOL = 1.25 mA, VDDIO = 3.3 V 0 0.4 V
Iin Input current SDA or SCL, Vin = VDDIO or GND –15 15 µA
Cin Input capacitance SDA or SCL <5 pF
(1) Specification is verified by characterization and is not tested in production.

6.8 Timing Requirements – DC and AC Serial Control Bus

Over 3.3-V supply and temperature ranges (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR SDA rise time (read) SDA, RPU = 10 kΩ, Cb ≤ 400 pF 40 ns
tF SDA fall time (read) SDA, RPU = 10 kΩ, Cb ≤ 400 pF 25 ns
tSU;DAT Set up time (read) 520 ns
tHD;DAT Hold up time (read) 55 ns
tSP Input filter 50 ns

6.9 Timing Requirements – Serializer for CLKIN

Over recommended operating supply and temperature ranges (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tTCP Transmit input CLKIN period 10 MHz to 75 MHz (see Figure 4) 13.3 T 100 ns
tTCIH Transmit input CLKIN high time 10 MHz to 75 MHz (see Figure 4) 0.4 × T 0.5 × T 0.6 × T ns
tTCIL Transmit input CLKIN low time 10 MHz to 75 MHz (see Figure 4) 0.4 × T 0.5 × T 0.6 × T ns
tCLKT CLKIN input transition time 10 MHz to 75 MHz (see Figure 4) 0.5 2.4 ns
SSCIN CLKIN input fmod (spread spectrum at 75 MHz) 35 kHz
fdev (spread spectrum at 75 MHz) ±2%

6.10 Timing Requirements – Serial Control Bus

Over recommended operating supply and temperature ranges (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
fSCL SCL clock frequency Standard mode 100 kHz
Fast mode 400
tLOW SCL low period Standard mode 4.7 μs
Fast mode 1.3
tHIGH SCL high period Standard mode 4 μs
Fast mode 0.6
tHD;STA Hold time for a start or a repeated start condition (see Figure 18) Standard mode 4 μs
Fast mode 0.6
tSU:STA Set up time for a start or a repeated start condition (see Figure 18) Standard mode 4.7 μs
Fast mode 0.6
tHD;DAT Data hold time
(see Figure 18)		 Standard mode 0 3.45 μs
Fast mode 0 0.9
tSU;DAT Data set up time
(see Figure 18)		 Standard mode 250 ns
Fast mode 100
tSU;STO Set up time for STOP condition
(see Figure 18)		 Standard mode 4 μs
Fast mode 0.6
tBUF Bus free time (between STOP and START; see Figure 18) Standard mode 4.7 μs
Fast mode 1.3
tr SCL and SDA rise time
(see Figure 18)		 Standard mode 1000 ns
Fast mode 300
tf SCL and SDA fall time
(see Figure 18)		 Standard mode 300 ns
Fast mode 300

6.11 Switching Characteristics – Serializer

Over recommended operating supply and temperature ranges (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tLHT Serializer output low-to-high transition time (see Figure 3) RL = 100 Ω, de-emphasis = disabled, VODSEL = 0 200 ps
RL = 100 Ω, de-emphasis = disabled, VODSEL = 1 200
tHLT Serializer output high-to-low transition time (see Figure 3) RL = 100 Ω, de-emphasis = disabled, VODSEL = 0 200 ps
RL = 100 Ω, de-emphasis = disabled, VODSEL = 1 200
tDIS Input data, setup time
(see Figure 4)		 DI[23:0], CI1, CI2, CI3 to CLKIN 2 ns
tDIH Input data, hold time
(see Figure 4)		 CLKIN to DI[23:0], CI1, CI2, CI3 2 ns
tXZD Serializer output active to OFF delay (see Figure 6)(1) 8 15 ns
tPLD Serializer PLL lock time
(see Figure 5)(1)(2)(3)		 RL = 100 Ω 1.4 10 ms
tSD Serializer delay, latency
(see Figure 7)(1)		 RL = 100 Ω 144 × T 145 × T ns
tDJIT Serializer output total jitter
(see Figure 8)		 RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 75 MHz 0.28 UI(4)
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 43 MHz 0.27
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 10 MHz 0.35
λSTXBW Serializer jitter transfer
(function –3 dB bandwidth)		 RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 75 MHz 3.3 MHz
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 43 MHz 2.3
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 10 MHz 0.8
δSTX Serializer jitter transfer
(function peaking)		 RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 75 MHz 0.86 dB
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 43 MHz 0.83
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 10 MHz 0.28
(1) Specification is verified by characterization and is not tested in production.
(2) tPLD and tDDLT is the time required by the serializer and deserializer, respectively, to obtain lock when exiting power-down state with an active clock.
(3) When the serializer output is at TRI-STATE the Deserializer loses PLL lock. Resynchronization and Re-lock must occur before data transfer require tPLD
(4) UI – Unit Interval is equivalent to one serialized data bit width (1 UI = 1 / [28 x CLK]). The UI scales with clock frequency.

6.12 Switching Characteristics – Deserializer

Over recommended operating supply and temperature ranges (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tRCP CLK output period tRCP = tTCP (CLKOUT) 13.3 T 100 ns
tRDC CLK output duty cycle CLKOUT SSCG = OFF, 10 to 75 MHz 40% 50% 60%
SSCG = ON, 10 to 20 MHz 35% 59% 65%
SSCG = ON, 10 to 65 MHz 40% 53% 60%
tCLH LVCMOS low-to-high transition time (see Figure 10) DO[23:0], CO1, CO2, CO3 VDDIO = 1.8 V, CL = 4 pF, OS_CLKOUT/DATA = L 2.1 ns
VDDIO = 3.3 V, CL = 4 pF, OS_CLKOUT/DATA = H 2
tCHL LVCMOS high-to-low transition time (see Figure 10) DO[23:0], CO1, CO2, CO3 VDDIO = 1.8 V, CL = 4 pF, OS_CLKOUT/DATA = L 1.6 ns
VDDIO = 3.3 V, CL = 4 pF, OS_CLKOUT/DATA = H 1.5
tROS Data valid before CLKOUT, setup time (see Figure 14) VDDIO = 1.71 to 1.89 V or 3 to 3.6 V, CL = 4 pF (lumped load), DO[23:0], CO1, CO2, CO3 0.23 × T 0.5 × T ns
tROH Data valid after CLKOUT, hold time (see Figure 14) VDDIO = 1.71 to 1.89 V or 3 to 3.6 V, CL = 4 pF (lumped load), DO[23:0], CO1, CO2, CO3 0.33 × T 0.5 × T ns
tDDLT Deserializer lock time
(see Figure 13)		 CLKOUT = 10 MHz, SSC[3:0] = OFF(1) 3 ms
CLKOUT = 75 MHz, SSC[3:0] = OFF(1) 4
CLKOUT = 10 MHz, SSC[3:0] = ON(1) 30
CLKOUT = 65 MHz, SSC[3:0] = ON(1) 6
tDD Deserializer delay, latency (see Figure 11) CLKOUT = 10 to 75 MHz, SSC[3:0] = OFF(2) 139 × T 140 × T ns
tDPJ Deserializer period jitter SSC[3:0] = OFF(3)(2) CLKOUT = 10 MHz 500 1000 ps
CLKOUT = 65 MHz 550 1250
CLKOUT = 75 MHz 435 900
tDCCJ Deserializer cycle-to-cycle jitter SSC[3:0] = OFF(4)(2)(5) CLKOUT = 10 MHz 375 900 ps
CLKOUT = 65 MHz 500 1150
CLKOUT = 75 MHz 460 1000
tIJT Deserializer input jitter tolerance (see Figure 16) EQ = OFF,
SSCG = OFF,
CLKOUT = 75 MHz		 jitter freq < 2 MHz 0.9 UI(6)
jitter freq > 6 MHz 0.5
BIST MODE
tPASS BIST PASS valid time
(see Figure 17)		 BISTEN = 1 1 10 μs
SSCG MODE
fDEV Spread spectrum clocking deviation frequency CLKOUT = 10 to 65 MHz, SSC[3:0] = ON ±0.5% ±2%
fMOD Spread spectrum clocking modulation frequency CLKOUT = 10 to 65 MHz, SSC[3:0] = ON 8 100 kHz
(1) tPLD and tDDLT is the time required by the serializer and deserializer, respectively, to obtain lock when exiting power-down state with an active clock.
(2) Specification is verified by design and is not tested in production.
(3) tDPJ is the maximum amount the period is allowed to deviate over many samples.
(4) Specification is verified by characterization and is not tested in production.
(5) tDCCJ is the maximum amount of jitter between adjacent clock cycles.
(6) UI – Unit Interval is equivalent to one serialized data bit width (1 UI = 1 / [28 x CLK]). The UI scales with clock frequency.
DS92LV2421 DS92LV2422 30110146.gif Figure 1. Serializer Test Circuit
DS92LV2421 DS92LV2422 30110130.gif Figure 2. Serializer Output Waveforms
DS92LV2421 DS92LV2422 30110147.gif Figure 3. Serializer Output Transition Times
DS92LV2421 DS92LV2422 30110131.gif Figure 4. Serializer Input CLKIN Waveform and Set and Hold Times
DS92LV2421 DS92LV2422 30110148.gif Figure 5. Serializer Lock Time
DS92LV2421 DS92LV2422 30110149.gif Figure 6. Serializer Disable Time
DS92LV2421 DS92LV2422 30110110.gif Figure 7. Serializer Latency Delay
DS92LV2421 DS92LV2422 30110150.gif Figure 8. Serializer Output Jitter
DS92LV2421 DS92LV2422 30110132.gif Figure 9. Checkerboard Data Pattern
DS92LV2421 DS92LV2422 30110105.gif Figure 10. Deserializer LVCMOS Transition Times
DS92LV2421 DS92LV2422 30110111.gif Figure 11. Deserializer Delay – Latency
DS92LV2421 DS92LV2422 30110113.gif Figure 12. Deserializer Disable Time (OSS_SEL = 0)
DS92LV2421 DS92LV2422 30110114.gif Figure 13. Deserializer PLL Lock Times and PDB Tri-State Delay
DS92LV2421 DS92LV2422 30110135.gif Figure 14. Deserializer Output Data Valid (Setup and Hold) Times With SSCG = Off
DS92LV2421 DS92LV2422 30110134.gif Figure 15. Deserializer Output Data Valid (Setup And Hold) Times With SSCG = On
DS92LV2421 DS92LV2422 30110116.gif Figure 16. Receiver Input Jitter Tolerance
DS92LV2421 DS92LV2422 30110152.gif Figure 17. BIST Pass Waveform
DS92LV2421 DS92LV2422 30110136.gif Figure 18. Serial Control Bus Timing Diagram

6.13 Typical Characteristics

DS92LV2421 DS92LV2422 Differential Output Voltage vs Ambient Temperature.gif Figure 19. Differential Output Voltage
vs Ambient Temperature
DS92LV2421 DS92LV2422 CMLOUT VOD vs Ambient Temperature.gif Figure 20. ROUT (CMLOUT) VOD
vs Ambient Temperature