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Product details

Parameters

Function Serializer Signal conditioning De-Emphasis EMI reduction VOD Control, SSC Compatible Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Display SerDes

Package | Pins | Size

WQFN (RHS) 48 49 mm² 7 x 7 open-in-new Find other Display SerDes

Features

  • 24-Bit Data, 3-Bit Control, 10- to 75-MHz Clock
  • AC-Coupled STP Interconnect Cable up to 10 m
  • Integrated Terminations on Serializer and
    Deserializer
  • At-Speed Link BIST Mode and Reporting Pin
  • Optional I2C-Compatible Serial Control Bus
  • Power-Down Mode Minimizes Power Dissipation
  • 1.8-V or 3.3-V Compatible LVCMOS I/O Interface
  • –40° to 85°C Temperature Range
  • >8-kV HBM
  • Serializer (DS92LV2421)
    • Data Scrambler for Reduced EMI
    • DC-Balance Encoder for AC Coupling
    • Selectable Output VOD and Adjustable
      De-emphasis
  • Deserializer (DS92LV2422)
    • Fast Random Data Lock; No Reference Clock
      Required
    • Adjustable Input Receiver Equalization
    • LOCK (Real-Time Link Status) Reporting Pin
    • EMI Minimization on Output Parallel Bus
      (SSCG)
    • Output Slew Control (OS)
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Description

The DS92LV242x chipset translates a parallel 24–bit LVCMOS data interface into a single high-speed CML serial interface with embedded clock information. This single serial stream eliminates skew issues between clock and data, reduces connector size, and reduces interconnect cost for transferring a 24-bit or less bus over FR-4 printed-circuit board backplanes and balanced cables. In addition, the DS92LV242x chipset also features a 3-bit control bus for slow speed signals. This allows for video and display applications with up to 24 bits per pixel (RGB).

Programmable transmit de-emphasis, receive equalization, on-chip scrambling, and DC balancing enables longer distance transmission over lossy cables and backplanes. The DS92LV2422 automatically locks to incoming data without an external reference clock or special sync patterns, providing easy plug-and-go operation. EMI is minimized by the use of low voltage differential signaling, receiver drive strength control, and spread spectrum clocking capability.

The DS92LV242x chipset is programmable though an I2C interface as well as through pins. A built-in, at-speed BIST feature validates link integrity and may be used for system diagnostics. The DS92LV2421 is offered in a 48-pin WQFN, and the DS92LV2422 is offered in a 60-pin WQFN package. Both devices operate over the full industrial temperature range of –40°C to 85°C.

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Download

Technical documentation

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$399.00
Description

The LV24EVK01 is an evaluation kit designed to demonstrate performance and capabilities of the DS92LV2421 and DS92LV2422 Channel Link II Serializer/Deserializer chipset.

The DS92LV2421 serializer board accepts LVCMOS input signals and provides a single serialized Channel Link II CML data pair as an (...)

Design tools & simulation

SIMULATION MODELS Download
SNLM126.ZIP (74 KB) - IBIS Model
SIMULATION TOOLS Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
WQFN (RHS) 48 View options

Ordering & quality

Support & training

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Videos

High-speed layout guidelines for reducing EMI in LVDS SerDes designs

This video provides guidelines on how to reduce EMI in designs that use TI serializers and deserializers.

Posted: 13-Jan-2018
Duration: 08:16

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