SLASE74F May   2015  – September 2016 HD3SS3212


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 High-Speed Performance Parameters
    7. 7.7 Switching Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Output Enable and Power Savings
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Down Facing Port for USB3.1 Type C
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
    3. 10.3 Systems Examples
      1. 10.3.1 Up Facing Port for USB3.1 Type C
      2. 10.3.2 PCIE/SATA/USB
      3. 10.3.3 PCIE/eSATA
      4. 10.3.4 USB/eSATA
      5. 10.3.5 MIPI Camera Serial Interface
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RKS|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The HD3SS3212 is a generic 2-channel high-speed mux/demux type of switch that can be used for routing high-speed signals between two different locations on a circuit board. The HD3SS3212 supports several high-speed data protocols with a differential amplitude of <1800 mVpp and a common mode voltage of <2.0 V, as with USB 3.0 and DisplayPort 1.2. The device’s one select input (SEL) pin can easily be controlled by an available GPIO pin within a system or from a microcontroller.

The HD3SS3212 with its adaptive common mode tracking technology can support applications where the common mode is different between the RX and TX pair. The two USB3.1 Type C connector applications show both a host and device side. The cable between the two connectors swivels the pairs to properly route the signals to the correct pin. The other applications are more generic because different connectors can be used.

Many interfaces require AC coupling between the transmitter and receiver. The 0402 capacitors are the preferred option to provide AC coupling; 0603 size capacitors also work. Avoid the 0805 size capacitors and C-packs. When placing AC coupling capacitors, symmetric placement is best. A capacitor value of 0.1 µF is best, and the value should match for the ±signal pair. The designer should place them along the TX pairs on the system board, which are usually routed on the top layer of the board.

The AC coupling capacitors have several placement options. Because the switch requires a bias voltage, the designer must place the capacitors on one side of the switch. If they are placed on both sides of the switch, a biasing voltage should be provided. Figure 4 shows a few placement options. The coupling capacitors are placed between the switch and endpoint. In this situation, the switch is biased by the system/host controller.

HD3SS3212 HD3SS3212I sch_ac_switch_ep_lase74.gif Figure 4. AC Coupling Capacitors between Switch TX and Endpoint TX

In Figure 5, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this situation, the switch on top is biased by the endpoint and the lower switch is biased by the host controller.

HD3SS3212 HD3SS3212I sch_ac_host_ep_lase74.gif Figure 5. AC Coupling Capacitors on Host TX and Endpoint TX

In the case where the common mode voltage in the system is higher than 2 V, the coupling capacitors are placed on both sides of the switch (shown in Figure 6). A biasing voltage of <2 V is required in this case.

HD3SS3212 HD3SS3212I sch_ac_both_lase74.gif
VBIAS can be GND
Capacitor and resistor values depend upon application
Figure 6. AC Coupling Capacitors on Both Sides of Switch

The HD3SS3212 can be used with the USB Type C connector to support the connector’s flip ability. Figure 7 provides the generic location for the AC coupling capacitors for this application.

HD3SS3212 HD3SS3212I sch_ac_for_USB_C_lase74.gif Figure 7. AC Coupling Capacitors for USB Type C

10.2 Typical Applications

10.2.1 Down Facing Port for USB3.1 Type C

HD3SS3212 HD3SS3212I app_down_facing_LASE74.gif Figure 8. Down Facing Port for USB3.1 Type C Connector Design Requirements

The HD3SS3212 can be designed into many different applications. All the applications have certain requirements for the system to work properly. The HD3SS3212 requires 3.3-V ±10% VCC rail. The OEn pin must be low for device to work otherwise it disables the outputs. This pin can be driven by a processor. The expectation is that one side of the device has AC coupling capacitors. Table 2 provides information on expected values to perform properly.

Table 2. Design Parameters

VCC 3.3 V
AXp/n, BXp/n, CXp/n CM input voltage 0 to 2 V
Control/OEn pin max voltage for low 0.8 V
Control/OEn pin min voltage for high 2.0 V
AC coupling capacitor 100 nF
RBIAS (Figure 8) when needed 1 kΩ Detailed Design Procedure

The HD3SS3212 is a high-speed passive switch device that can behave as a mux or demux. Because this is a passive switch, signal integrity is important because the device provides no signal conditioning capability. The device can support 2 to 3 inches of board trace and a connector on either end.

To design in the HD3SS3212, the designer needs to understand the following.

  • Determine the loss profile between circuits that are to be muxed or demuxed.
  • Provide clean impedance and electrical length matched board traces.
  • Depending upon the application, determine the best place to put the 100-nF coupling capacitor.
  • Provide a control signal for the SEL and OEn pins.
  • The thermal pad must be connected to ground.
  • See the application schematics on recommended decouple capacitors from VCC pins to ground Application Curves

HD3SS3212 HD3SS3212I app_eye_01_LASE74.gif Figure 9. 10 Gbps Source Eye Diagram
HD3SS3212 HD3SS3212I app_eye_02_LASE74.gif Figure 10. 10 Gbps Output Eye Diagram

10.3 Systems Examples

10.3.1 Up Facing Port for USB3.1 Type C

HD3SS3212 HD3SS3212I app_up_facing_LASE74.gif Figure 11. Up Facing Port for USB3.1 USB Type-C Connector


HD3SS3212 HD3SS3212I app_PCIE_mthrbd_LASE74.gif Figure 12. PCIE Motherboard

10.3.3 PCIE/eSATA

HD3SS3212 HD3SS3212I app_PCIE_eSATA_LASE74.gif Figure 13. PCIE and eSATA Combo

10.3.4 USB/eSATA

HD3SS3212 HD3SS3212I app_eSATA_USB3_LASE74.gif Figure 14. eSATA and USB 3.0 Combo Connector

10.3.5 MIPI Camera Serial Interface

HD3SS3212 HD3SS3212I app_CSI_camera_LASE74.gif Figure 15. CSI Camera Array