SBOS115A June   1999  – March 2025 INA133 , INA2133

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Gain Error and Drift
      2. 6.3.2 Input Voltage Range
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Operating Voltage
      2. 7.1.2 Input Voltage
      3. 7.1.3 Offset Voltage Trim
    2. 7.2 Typical Application
    3. 7.3 Additional Applications
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Examples
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI (Free Software Download)
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application Information

The INA133 and INA2133 are high-speed difference amplifiers are designed for a wide range of general-purpose applications. Figure 7-2 shows the basic connections required for operation of the INA133. Place decoupling capacitors close to the device pins as shown in Figure 7-2 in applications with noisy or high impedance power supplies. All circuitry is completely independent in the dual version to provide lowest crosstalk and normal behavior when one amplifier is overdriven or short-circuited.

As shown in Figure 7-2, the differential input signal is connected to pins 2 and 3. The source impedances connected to the inputs must be nearly equal to maintain good common-mode rejection. A 5Ω mismatch in source impedance degrades the common-mode rejection of a typical device to approximately 80dB (a 10Ω mismatch degrades CMR to 74dB). If the source has a known impedance mismatch, an additional resistor in series with the opposite input can be used to preserve good common-mode rejection.

The internal resistors of the INA133 are accurately ratio trimmed to match. That is, R1 is trimmed to match R2 and R3 is trimmed to match R4. However, the absolute values may not be equal (R1 + R2 may be slightly different than R3 + R4). Thus, large series resistors on the input (greater than 250Ω), even if well matched, can degrade common-mode rejection.

Circuit board layout constraints can suggest possible variations in connections of the internal resistors, like that pins 1 and 3 can be interchanged. However, because of the ratio trimming technique used, CMRR can degrade. If pins 1 and 3 are interchanged, pins 2 and 5 must also be interchanged to maintain proper ratio matching.