SBOS115A June   1999  – March 2025 INA133 , INA2133

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Gain Error and Drift
      2. 6.3.2 Input Voltage Range
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Operating Voltage
      2. 7.1.2 Input Voltage
      3. 7.1.3 Offset Voltage Trim
    2. 7.2 Typical Application
    3. 7.3 Additional Applications
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI (Free Software Download)
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Power Supply Recommendations

The nominal performance of the INA105 is specified with a supply voltage of ±15V or ±5V. The device operates using power supplies from ±2.25V to ±18V with varying performance. Parameters varying across the operating voltage and reference voltage range can be referenced in the Typical Characteristics.

TI highly recommends to add low-ESR ceramic bypass capacitors (CBYP) between each supply pin and ground. Only one CBYP is sufficient for single supply operation. Place the CBYP as close to the device as possible to reduce coupling errors from noisy or high-impedance power supplies. Route the power supply trace through CBYP before reaching the device power supply terminals. For more information, see Layout Guidelines.