SBOS115A June 1999 – March 2025 INA133 , INA2133
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Detailed Description
- 7 Application and Implementation
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
Package Options
Refer to the PDF data sheet for device specific package drawings
Mechanical Data (Package|Pins)
- D|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information
5.5 Typical Characteristics
At TA = +25°C, VS = ±15V, RL = 10kΩ connected to ground, and VREF = 0V, unless otherwise noted.
Figure 5-1 Gain vs Frequency
Figure 5-3 Power Supply Rejection vs Frequency
Figure 5-5 Input Common-Mode Voltage vs Output Voltage
Figure 5-7 Voltage Noise Density vs Frequency
Figure 5-9 Quiescent Current vs Temperature
Figure 5-11 Short-Circuit Current vs Temperature
Figure 5-13 Offset Voltage Production Distribution VS = ±15V
Figure 5-15 Offset Voltage Drift Production Distribution VS = ±15V
Figure 5-17 Small-Signal Overshoot vs Load Capacitance
Figure 5-19 Small-Signal Step Response
Figure 5-21 Maximum Output Voltage vs Frequency
Figure 5-2 Common-Mode Rejection vs Frequency
Figure 5-4 Channel Separation vs Frequency
Figure 5-6 Total Harmonic Distortion + Noise vs Frequency
Figure 5-8 0.1Hz to 10Hz Peak-to-Peak Voltage Noise
Figure 5-10 Slew Rate vs Temperature
Figure 5-12 Output Voltage Swing vs Output Current
Figure 5-14 Offset Voltage Production Distribution VS = ±5V
Figure 5-16 Offset Voltage Drift Production Distribution VS = ±5V
Figure 5-18 Settling Time vs Load Capacitance
Figure 5-20 Large-Signal Step Response