SBOS601A February   2012  – December 2021 INA230

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements (I2C)
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Basic ADC Functions
      2. 8.3.2 Power Calculation
      3. 8.3.3 Alert Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Averaging and Conversion Time Considerations
      2. 8.4.2 Filtering and Input Considerations
    5. 8.5 Programming
      1. 8.5.1 Programming the Calibration Register
      2. 8.5.2 Programming the INA230 Power Measurement Engine
        1. 8.5.2.1 Calibration Register and Scaling
      3. 8.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)
      4. 8.5.4 Default INA230 Settings
      5. 8.5.5 Bus Overview
        1. 8.5.5.1 Serial Bus Address
        2. 8.5.5.2 Serial Interface
      6. 8.5.6 Writing to and Reading From the I2C Serial Interface
        1. 8.5.6.1 High-Speed I2C Mode
      7. 8.5.7 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Configuration Register (00h, Read/Write)
      2. 8.6.2 AVG Bit Settings [11:9]
      3. 8.6.3 VBUS CT Bit Settings [8:6]
      4. 8.6.4 VSH CT Bit Settings [5:3]
      5. 8.6.5 Mode Settings [2:0]
      6. 8.6.6 Data Output Register
        1. 8.6.6.1 Shunt Voltage Register (01h, Read-Only)
        2. 8.6.6.2 Bus Voltage Register (02h, Read-Only) (1)
        3. 8.6.6.3 Power Register (03h, Read-Only)
        4. 8.6.6.4 Current Register (04h, Read-Only)
        5. 8.6.6.5 Calibration Register (05h, Read/Write)
        6. 8.6.6.6 Mask/Enable Register (06h, Read/Write)
        7. 8.6.6.7 Alert Limit Register (07h, Read/Write)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 High-Side Sensing Circuit Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
  • DGS|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.1 Configuration Register (00h, Read/Write)

Table 8-4 Configuration Register (00h, Read/Write) Description
BIT #D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
BIT
NAME		RST———AVG2AVG1AVG0VBUSCT2VBUSCT1VBUSCT0VSHCT2VSHCT1VSHCT0MODE3MODE2MODE1
POR VALUE0100000100100111

The Configuration register settings control the operating modes for the INA230. This register controls the conversion time settings for both the shunt and bus voltage measurements, as well as the averaging mode used. The operating mode that controls which signals are selected to be measured is also programmed in the Configuration register.

The Configuration register can be read from at any time without impacting or affecting the device settings or a conversion in progress. Writing to the Configuration register halts any conversion in progress until the write sequence is complete, resulting in the start of a new conversion based on the new contents of the Configuration register. This feature prevents any uncertainty in the conditions used for the next completed conversion.

RST:Reset Bit
Bit 15Setting this bit to '1' generates a system reset that is the same as a power-on reset; all registers are reset to default values. This bit self-clears.
AVG:Averaging Mode
Bits 9–11Sets the number of samples that are collected and averaged together. Table 8-5 summarizes the AVG bit settings and related number of averages for each bit.