SBOSAA0C november   2021  – may 2023 INA350

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Gain-Setting
        1. 8.3.1.1 Gain Error and Drift
      2. 8.3.2 Input Common-Mode Voltage Range
      3. 8.3.3 EMI Rejection
      4. 8.3.4 Typical Specifications and Distributions
      5. 8.3.5 Electrical Overstress
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Reference Pin
      2. 9.1.2 Input Bias Current Return Path
    2. 9.2 Typical Applications
      1. 9.2.1 Resistive-Bridge Pressure Sensor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Typical Characteristics

at TA = 25°C, VS = (V+) – (V–) = 5.5 V, VIN = (VIN+) – (VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) + (VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)

GUID-20220323-SS0I-NG9D-RDPQ-12XKKPXJ7HKS-low.gif
G = 10, 20, 30, 50 N = 140 μ = 18 μV σ = 0.185 mV
Figure 7-1 Typical Distribution of Input Referred Offset Voltage
GUID-20211207-SS0I-TFMB-T4Z9-RJNHVDPK7P4N-low.gif
TA = 25°C N = 72 μ = 0.40 pA σ = 0.15 pA
Figure 7-3 Typical Distribution of Input Bias Current
GUID-20211206-SS0I-ZZGT-1NX7-MTQ33QMWV8MV-low.gif
TA = 85°C N = 72 μ = 22 pA σ = 0.95 pA
Figure 7-5 Typical Distribution of Input Bias Current
GUID-20211206-SS0I-6F3M-2G8N-FHFNSG93NHZR-low.gif
G = 10 N = 36 μ = 2.50 μV/V σ = 8.92 μV/V
Figure 7-7 Typical Distribution of CMRR
GUID-20220323-SS0I-MBS3-XBL6-V8QWHG2XCGLD-low.gif
G = 30 N = 34 μ = –1.05 μV/V σ = 6.85 μV/V
Figure 7-9 Typical Distribution of CMRR
GUID-20220323-SS0I-JNCT-RDCB-3VTQKSLMMFTZ-low.gif
G = 10, 20, 30, 50
Figure 7-11 Input Referred Offset Voltage vs Temperature
GUID-20211209-SS0I-PCJ1-63SC-9B6XZN6ZNQZD-low.gif
Figure 7-13 Input Offset Current vs Temperature
GUID-20211207-SS0I-KXMR-DX18-VDBBPTCCZWQ0-low.gif
Figure 7-15 Shutdown Quiescent Current vs Temperature
GUID-20220323-SS0I-HS5N-F4M3-C4LZLW8NX8NJ-low.gif
Figure 7-17 Gain Error vs Temperature
GUID-20211206-SS0I-GCLP-P5LD-MZT3GTBBJMT1-low.gif
V+ = 2.75 V and V– = –2.75 V
Figure 7-19 Input Referred Offset Voltage vs Input Common-Mode Voltage
GUID-20211206-SS0I-3ZVG-89X8-MDHPFB6ZBHPS-low.gif
V+ = 2.75 V and V– = –2.75 V
Figure 7-21 Input Bias Current vs Input Common-Mode Voltage
GUID-20211206-SS0I-BGDJ-JNGN-PP9J0XHXFLCN-low.gif
V+ = 2.75 V and V– = –2.75 V
Figure 7-23 Quiescent Current vs Input Common-Mode Voltage
GUID-20211207-SS0I-SD41-76RZ-S91T8W4S5KFD-low.gif
Figure 7-25 Quiescent Current vs Supply Voltage
GUID-20211207-SS0I-NP47-N339-ZTDZ9D0LX76H-low.gif
Figure 7-27 Output Voltage vs Output Current (Sinking)
GUID-20220323-SS0I-JKKN-QMHH-5QZRQD3M1NXW-low.gif
Figure 7-29 CMRR (Referred to Input) vs Frequency
GUID-20220323-SS0I-F9PQ-ZXWN-JFPVT2PS8NL4-low.gif
Figure 7-31 PSRR– (Referred to Input) Vs Frequency
GUID-20211207-SS0I-ZVTX-RS7B-XDD2RCZMQBC2-low.gif
Figure 7-33 0.1 Hz to 10 Hz Voltage Noise in Time Domain
GUID-20211207-SS0I-FVVS-BQXJ-8PC5MSSLTH2X-low.gif
 
 
Figure 7-35 Maximum Output Voltage vs Frequency
GUID-20211207-SS0I-BSNG-XSF6-BM5LPDZNXDNQ-low.gif
VS = 5.5 V BW = 80 kHz VCM = 2.75 V
RL = 100 kΩ VOUT = 1 VRMS
Figure 7-37 THD + N Frequency
GUID-20211207-SS0I-H1KZ-ZVGD-4GLFKNVGQCMX-low.gif
VS = 5.5 V G = 10 VOUT = 100 mVPP
Figure 7-39 Small-Signal Overshoot vs Capacitive Load
GUID-20211207-SS0I-PM2V-MC3N-SDLVBXT969DZ-low.gif
V+ = 2.75 V V– = –2.75 V G = 10 VOUT = 4 VPP
Figure 7-41 Large Signal Step Response
GUID-20211207-SS0I-R1LT-BG8P-WSF3KHMWVK6B-low.gif
V+ = 2.75 V V– = –2.75 V G = 10 VOUT = 4 VPP
Figure 7-43 Large Signal Settling Time (Rising Edge)
GUID-20211207-SS0I-QFWJ-HR5D-8TW7NB8PDWGM-low.gif
V+ = 2.75 V V– = –2.75 V G = 10 VOUT = 0.1 VPP
Figure 7-45 Small-Signal Step Response
GUID-20211209-SS0I-1WX7-BB11-CC5MGML84GGL-low.gif
V+ = 2.75 V V– = –2.75 V G = 10 VIN = 1 VPP
Figure 7-47 Over-Load Recovery (Rising Edge)
GUID-20211207-SS0I-SP1N-JDX1-9TBJLTPWCHSQ-low.gif
V+ = 2.75 V V– = –2.75 V G = 10 VIN = 0.6 VPP
Figure 7-49 No Phase Reversal
GUID-20211207-SS0I-TLSJ-5G7W-1VZXSTMFFC8G-low.gif
V+ = +2.75 V V– = –2.75 V G = 10
Figure 7-51 Disable Response
GUID-20211209-SS0I-RXRC-VWX8-FVRLFG1VRGZQ-low.gif
VS = 5.5 V G = 10, 20, 30, 50 VREF = VS / 2
Figure 7-53 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)
GUID-20211209-SS0I-NFX3-JKDZ-NCPHMXN4RRXL-low.gif
VS = 5.5 V G = 10, 20, 30, 50 VREF = 0 V
Figure 7-55 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)
GUID-20211209-SS0I-X6ZV-FKVG-J9TVFJ27LG9T-low.gif
VS = 5.5 V G = 10, 20, 30, 50 VREF = VS / 2
Figure 7-57 Input Common-Mode Voltage vs Output Voltage
GUID-20211209-SS0I-DRRF-GFNL-LL9VZGC63W6R-low.gif
VS = 5.5 V G = 10, 20, 30, 50 VREF = 0 V
Figure 7-59 Input Common-Mode Voltage vs Output Voltage
GUID-20220323-SS0I-QZHK-KTHC-WT0M3THV71S3-low.gif
G = 10, 20, 30, 50 N = 140 μ = 0.37 μV/°C σ = 0.23 μV/°C
Figure 7-2 Typical Distribution of Input Referred Offset Drift
GUID-20211207-SS0I-MW56-CHKM-CNM5ZMZ40ZH8-low.gif
TA = 25°C N = 36 μ = –0.03 pA σ = 0.23 pA
Figure 7-4 Typical Distribution of Input Offset Current
GUID-20211206-SS0I-NT6N-0VQV-RRQLRNRNTHKR-low.gif
TA = 85°C N = 36 μ = –1 pA σ = 1 pA
Figure 7-6 Typical Distribution of Input Offset Current
GUID-20211206-SS0I-KS84-BJTF-C5PBK2DVNPDR-low.gif
G = 20 N = 36 μ = 2.33 μV/V σ = 8.45 μV/V
Figure 7-8 Typical Distribution of CMRR
GUID-20220323-SS0I-X7VB-LRRR-TQHBRGDWJFM7-low.gif
G = 50 N = 34 μ = –1.43 μV/V σ = 6.62 μV/V
Figure 7-10 Typical Distribution of CMRR
GUID-20211207-SS0I-JKPZ-CHDF-QNTQFQHF4HVT-low.gif
Figure 7-12 Input Bias Current vs Temperature
GUID-20211207-SS0I-R3HF-7ZDW-NXPPKXFDGNFV-low.gif
Figure 7-14 Quiescent Current vs Temperature
GUID-20211207-SS0I-D6TH-NWVH-CDQ1BFXBV0B5-low.gif
Figure 7-16 Short Circuit Current vs Temperature
GUID-20220323-SS0I-Z61D-Z4L0-STVGW8QCQ81V-low.gif
 
Figure 7-18 CMRR vs Temperature
GUID-20211206-SS0I-M48Z-HTBD-74CV7TGZDRS9-low.gif
V+ = 1.65 V and V– = –1.65 V
Figure 7-20 Input Referred Offset Voltage vs Input Common-Mode Voltage
GUID-20211209-SS0I-QP12-G1X8-0ZLL3J9D8RJV-low.gif
V+ = 2.75 V and V– = –2.75 V
Figure 7-22 Input Offset Current vs Input Common-Mode Voltage
GUID-20211207-SS0I-S9VV-R7TC-QKZNSTKKGFS2-low.gif
G =  10
Figure 7-24 Input Referred Offset Voltage vs Supply Voltage
GUID-20211207-SS0I-PGNB-CGLG-5LZ5WQQRNZVX-low.gif
Figure 7-26 Output Voltage vs Output Current (Sourcing)
GUID-20220323-SS0I-N8DL-NV8Z-WPKNXTMD8T6W-low.gif
Figure 7-28 Closed-Loop Gain vs Frequency
GUID-20220323-SS0I-J8S0-MBWK-0C71JD88ZCHD-low.gif
Figure 7-30 PSRR+ (Referred to Input) vs Frequency
GUID-20220323-SS0I-9M7W-ZZXD-T68RRFHLXL6P-low.gif
Figure 7-32 Input Referred Voltage Noise Spectral Density
GUID-20211207-SS0I-7BS7-P6DK-47M6LN3MCQK1-low.gif
Figure 7-34 Closed-Loop Output Impedance vs Frequency
GUID-20211207-SS0I-J7JJ-NX0Z-NS13H3GGLWWZ-low.gif
VS = 5.5 V BW = 80 kHz VCM = 2.75 V
RL = 10 kΩ VOUT = 0.5 VRMS
Figure 7-36 THD + N Frequency
GUID-20211207-SS0I-PDFT-XWQ5-TNJHVBRQPT8F-low.gif
 
 
Figure 7-38 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency
GUID-20211207-SS0I-NV6B-KLHP-0MKPS2RRZLQJ-low.gif
VS = 5.5 V G = 20 VOUT = 100 mVPP
Figure 7-40 Small-Signal Overshoot vs Capacitive Load
GUID-20211207-SS0I-BS5L-20KD-SXM8NMPM66CZ-low.gif
V+ = 2.75 V V– = –2.75 V G = 10 VOUT = 4 VPP
Figure 7-42 Large Signal Settling Time (Falling Edge)
GUID-20220323-SS0I-QTKK-GNZ9-M87PCGTCTN6D-low.gif
V+ = 2.75 V V– = –2.75 V G = 50 VOUT = 4 VPP
Figure 7-44 Large Signal Step Response
GUID-20220323-SS0I-FJGQ-BPBW-6LLD14X3XNBN-low.gif
V+ = 2.75 V V– = –2.75 V G = 50 VOUT = 0.1 VPP
Figure 7-46 Small-Signal Step Response
GUID-20211209-SS0I-ZMFZ-8GK7-DHTGJVTP9HWC-low.gif
V+ = 2.75 V V– = –2.75 V G = 10 VIN = 1 VPP
Figure 7-48 Over-Load Recovery (Falling Edge)
GUID-20211207-SS0I-TSLM-W84V-NLGM2QMZHT6X-low.gif
V+ = +2.75 V V– = –2.75 V G = 10
Figure 7-50 Enable Response
GUID-20211209-SS0I-HSGK-3RDH-QDQTTRP0QPLT-low.gif
VS = 3.3 V G = 10, 20, 30, 50 VREF = VS / 2
Figure 7-52 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)
GUID-20211209-SS0I-T1LQ-PFFP-9K8CPPQMLJ7N-low.gif
VS = 3.3 V G = 10, 20, 30, 50 VREF = 0 V
Figure 7-54 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)
GUID-20211209-SS0I-HLSV-36F2-TDDTKBDBJHVC-low.gif
VS = 3.3 V G = 10, 20, 30, 50 VREF = VS / 2
Figure 7-56 Input Common-Mode Voltage vs Output Voltage
GUID-20211209-SS0I-GLFG-3GDS-0HQ7463VBHN7-low.gif
VS = 3.3 V G = 10, 20, 30, 50 VREF = 0 V
Figure 7-58 Input Common-Mode Voltage vs Output Voltage